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--Nama file : reg16x.vbe
--Deskripsi : blok register 16 bit
--Author    : Mas Adit
--Tanggal  : 24 Agustus 2001

entity reg16x is
port (
        a : in bit_vector(15 downto 0);
        en : in bit;
        clr : in bit;
        b : out bit_vector(15 downto 0);
        vdd : in bit;
        vss : in bit
);
end reg16x;

architecture vbe of reg16x is

signal temp : bit_vector(15 downto 0);
signal reg : reg_vector(15 downto 0) register;
constant nol : bit_vector(15 downto 0) := "0000000000000000";

begin

        flip_flop : block ((en = '1') and not(en'STABLE))
        begin
               reg <= guarded a;
        end block;

        temp <= nol when (clr = '1')
                    else reg;

        b <= temp;

        assert ((vdd = '1') and (vss = '0'))
        report "power supply is missing on reg15x"
        severity warning;

end vbe;