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-- VHDL data flow description generated from `substract`
--              date : Mon Jul 30 16:47:36 2001


-- Entity Declaration

ENTITY substract IS
  PORT (
  a : in BIT;   -- a
  b : in BIT;   -- b
  bin : in BIT; -- bin
  diff : out BIT;       -- diff
  bout : out BIT;       -- bout
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END substract;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF substract IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on substractx"
    SEVERITY WARNING;


bout <= ((not (a) and b) or (bin and (not (a) or b)));

diff <= (a xor b xor bin);
END;