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-- VHDL data flow description generated from `zero16`
--              date : Mon Jul 30 17:40:21 2001


-- Entity Declaration

ENTITY zero16 IS
  PORT (
  a : out bit_vector(15 DOWNTO 0) ;     -- a
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END zero16;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF zero16 IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on zero16x"
    SEVERITY WARNING;


a (0) <= '0';

a (1) <= '0';

a (2) <= '0';

a (3) <= '0';

a (4) <= '0';

a (5) <= '0';

a (6) <= '0';

a (7) <= '0';

a (8) <= '0';

a (9) <= '0';

a (10) <= '0';

a (11) <= '0';

a (12) <= '0';

a (13) <= '0';

a (14) <= '0';

a (15) <= '0';
END;