Subversion Repositories idea

-- VHDL data flow description generated from `cfb_bop`
--              date : Sat Sep  1 20:22:55 2001


-- Entity Declaration

ENTITY cfb_bop IS
  PORT (
  vss : in BIT; -- vss
  vdd : in BIT; -- vdd
  sel3 : out bit_vector(0 TO 1) ;       -- sel3
  sel2 : out bit_vector(0 TO 1) ;       -- sel2
  sel1 : out bit_vector(0 TO 1) ;       -- sel1
  en_out : out BIT;     -- en_out
  en_rcbc : out BIT;    -- en_rcbc
  en_iv : out BIT;      -- en_iv
  en_in : out BIT;      -- en_in
  cke_b_mode : out BIT; -- cke_b_mode
  cp_ready : out BIT;   -- cp_ready
  emp_buf : out BIT;    -- emp_buf
  s_gen_key : out BIT;  -- s_gen_key
  s_mesin : out BIT;    -- s_mesin
  e_mesin : out BIT;    -- e_mesin
  first_dt : inout BIT; -- first_dt
  e : in BIT;   -- e
  finish : in BIT;      -- finish
  dt_ready : in BIT;    -- dt_ready
  key_ready : in BIT;   -- key_ready
  clk : in BIT; -- clk
  active : in BIT       -- active
  );
END cfb_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF cfb_bop IS
  SIGNAL current_state : REG_VECTOR(0 TO 3) REGISTER;   -- current_state
  SIGNAL aux7 : BIT;            -- aux7
  SIGNAL aux6 : BIT;            -- aux6
  SIGNAL aux5 : BIT;            -- aux5
  SIGNAL aux3 : BIT;            -- aux3
  SIGNAL aux0 : BIT;            -- aux0
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL next_state_s7 : BIT;           -- next_state_s7
  SIGNAL current_state_s7 : BIT;                -- current_state_s7
  SIGNAL current_state_s8 : BIT;                -- current_state_s8
  SIGNAL next_state_s9 : BIT;           -- next_state_s9
  SIGNAL current_state_s9 : BIT;                -- current_state_s9
  SIGNAL next_state_s11 : BIT;          -- next_state_s11
  SIGNAL next_state_s12 : BIT;          -- next_state_s12
  SIGNAL current_state_s12 : BIT;               -- current_state_s12
  SIGNAL aux18 : BIT;           -- aux18
  SIGNAL aux19 : BIT;           -- aux19
  SIGNAL aux20 : BIT;           -- aux20
  SIGNAL aux22 : BIT;           -- aux22
  SIGNAL aux25 : BIT;           -- aux25

BEGIN
  aux25 <= (current_state_s12 or next_state_s11 or (e and current_state_s9));
  aux22 <= (not ((dt_ready and finish)) and current_state_s8);
  aux20 <= (current_state_s9 or current_state_s7 or current_state_s8 or
current_state_s6 or aux19);
  aux19 <= ((current_state (1) and current_state (3) and current_state (0))
or (current_state (2) and current_state (3) and current_state
(0)) or current_state_s12 or aux18);
  aux18 <= ((not (current_state (0)) and not (current_state (3)) and not
(current_state (1)) and current_state (2)) or (current_state
(0) and current_state (3) and not (current_state (2)) and not
(current_state (1))));
  current_state_s12 <= (not (current_state (0)) and not (current_state (3)) and current_state
(2) and current_state (1));
  next_state_s12 <= ((current_state (1) and current_state (3) and current_state (0))
or (current_state (2) and current_state (3) and current_state
(0)));
  next_state_s11 <= (not (e) and current_state_s9);
  current_state_s9 <= (current_state (3) and current_state (2) and current_state (1));
  next_state_s9 <= (dt_ready and finish and current_state_s8);
  current_state_s8 <= (not (current_state (0)) and current_state (3) and not (current_state
(2)) and not (current_state (1)));
  current_state_s7 <= (not (current_state (2)) and current_state (1) and not (current_state
(0)) and current_state (3));
  next_state_s7 <= (current_state_s6 or current_state_s4);
  current_state_s6 <= (current_state (0) and not (current_state (3)) and not (current_state
(2)) and current_state (1));
  current_state_s5 <= (not (current_state (0)) and not (current_state (3)) and not
(current_state (2)) and current_state (1));
  current_state_s4 <= (current_state (0) and not (current_state (3)) and not (current_state
(1)) and current_state (2));
  current_state_s3 <= (current_state (0) and not (current_state (3)) and not (current_state
(2)) and not (current_state (1)));
  current_state_s2 <= (not (current_state (1)) and current_state (2) and not (current_state
(0)) and current_state (3));
  next_state_s2 <= (not ((not (dt_ready) or not (key_ready) or not (first_dt)))
and current_state_s1);
  current_state_s1 <= (not (current_state (0)) and not (current_state (3)) and not
(current_state (2)) and not (current_state (1)));
  aux0 <= (active or (current_state (0) and current_state (2) and current_state
(1)));
  aux3 <= (current_state_s4 or current_state_s3 or current_state_s2 or
current_state_s1 or aux0);
  aux5 <= (not (active) and (current_state_s2 or (current_state (0) and
current_state (2) and current_state (1)) or current_state_s4
or current_state_s3 or current_state_s1 or current_state_s5
or aux20));
  aux6 <= (not (active) and (current_state_s9 or next_state_s9 or next_state_s2));
  aux7 <= (not (first_dt) and key_ready and dt_ready and current_state_s1);
  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (3) <= GUARDED (not (active) and (current_state_s7 or next_state_s9 or next_state_s7
or next_state_s2 or aux22 or aux25));
  END BLOCK label0;
  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED (active or current_state_s3 or next_state_s12 or (e and current_state_s9)
or next_state_s9 or next_state_s2 or aux18);
  END BLOCK label1;
  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED (active or current_state_s5 or next_state_s12 or next_state_s11
or next_state_s9 or next_state_s7 or aux7);
  END BLOCK label2;
  label3 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED (active or current_state_s2 or current_state_s5 or current_state_s3
or aux25);
  END BLOCK label3;

first_dt <= (current_state_s5 or current_state_s1 or aux0);

e_mesin <= (current_state_s5 or aux3 or aux20);

s_mesin <= ((not (active) and aux22) or (not (active) and (current_state_s7
or next_state_s7)));

s_gen_key <= aux5;

emp_buf <= aux6;

cp_ready <= (not (active) and current_state_s12);

cke_b_mode <= aux5;

en_in <= aux6;

en_iv <= (not (active) and (current_state_s2 or aux7));

en_rcbc <= '0';

en_out <= (not (active) and next_state_s12);

sel1 (1) <= (current_state_s7 or current_state_s8 or current_state_s6 or
current_state_s5 or current_state_s4 or current_state_s3 or
aux0 or ((not (dt_ready) or not (key_ready) or not (first_dt))
and current_state_s1) or aux19);

sel1 (0) <= ((not (active) and next_state_s11) or (not (active) and (current_state_s2
or next_state_s2)));

sel2 (1) <= (current_state_s4 or current_state_s2 or current_state_s1 or
aux0 or aux20);

sel2 (0) <= (not (active) and (current_state_s5 or current_state_s3));

sel3 (1) <= (current_state_s6 or aux19 or aux3);

sel3 (0) <= (not (active) and (current_state_s9 or current_state_s7 or current_state_s8
or current_state_s5));
END;