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-- File Name    : dec_mode.vbe
-- Version      : v1.1
-- Description  : behavioral description of decoder mode
-- Purpose      : to generate structural description of decoder mode
-- Author       : Sigit Dewantoro
-- Address      : IS Laboratory, Labtek VIII, ITB, Jl. Ganesha 10, Bandung, Indonesia
-- Email        : sigit@students.ee.itb.ac.id, sigit@ic.vlsi.itb.ac.id
-- Date         : August 12th, 2001

entity dec_mode is
port(
        start : in bit;
        mode  : in bit_vector (1 downto 0);
        ecb   : out bit;
        cbc   : out bit;
        cfb   : out bit;
        ofb   : out bit;
        vdd   : in bit;
        vss   : in bit
);
end dec_mode;

architecture vbe of dec_mode is
        SIGNAL  ecb_reg   : BIT;
        SIGNAL  cbc_reg   : BIT;
        SIGNAL  cfb_reg   : BIT;
        SIGNAL  ofb_reg   : BIT;

begin
ASSERT ((vdd and not (vss)) = '1')
  REPORT "power supply is missing on dec_mode"
  SEVERITY WARNING;

        ecb_reg <= '1' when (mode = "00") else '0';
        cbc_reg <= '1' when (mode = "01") else '0';
        cfb_reg <= '1' when (mode = "10") else '0';
        ofb_reg <= '1' when (mode = "11") else '0';

        ecb <= ecb_reg when start else '0';
        cbc <= cbc_reg when start else '0';
        cfb <= cfb_reg when start else '0';
        ofb <= ofb_reg when start else '0';

end vbe;