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-- VHDL data flow description generated from `ecb`
--              date : Sat Sep  1 20:14:57 2001


-- Entity Declaration

ENTITY ecb IS
  PORT (
  active : in BIT;      -- active
  clk : in BIT; -- clk
  cke : in BIT; -- cke
  key_ready : in BIT;   -- key_ready
  finish : in BIT;      -- finish
  req_cp : in BIT;      -- req_cp
  e : in BIT;   -- e
  e_mesin : out BIT;    -- e_mesin
  s_mesin : out BIT;    -- s_mesin
  s_gen_key : out BIT;  -- s_gen_key
  emp_buf : out BIT;    -- emp_buf
  cp_ready : out BIT;   -- cp_ready
  cke_b_mode : out BIT; -- cke_b_mode
  en_in : out BIT;      -- en_in
  en_iv : out BIT;      -- en_iv
  en_rcbc : out BIT;    -- en_rcbc
  en_out : out BIT;     -- en_out
  sel1 : out bit_vector(1 DOWNTO 0) ;   -- sel1
  sel2 : out bit_vector(1 DOWNTO 0) ;   -- sel2
  sel3 : out bit_vector(1 DOWNTO 0) ;   -- sel3
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END ecb;


-- Architecture Declaration

ARCHITECTURE VBE OF ecb IS
  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL current_state_s6 : BIT;                -- current_state_s6
  SIGNAL next_state_s6 : BIT;           -- next_state_s6
  SIGNAL current_state_s5 : BIT;                -- current_state_s5
  SIGNAL next_state_s5 : BIT;           -- next_state_s5
  SIGNAL current_state_s4 : BIT;                -- current_state_s4
  SIGNAL next_state_s4 : BIT;           -- next_state_s4
  SIGNAL current_state_s3 : BIT;                -- current_state_s3
  SIGNAL next_state_s3 : BIT;           -- next_state_s3
  SIGNAL current_state_s2 : BIT;                -- current_state_s2
  SIGNAL next_state_s2 : BIT;           -- next_state_s2
  SIGNAL current_state_s1 : BIT;                -- current_state_s1
  SIGNAL next_state_s1 : BIT;           -- next_state_s1
  SIGNAL current_state_s0 : BIT;                -- current_state_s0
  SIGNAL next_state_s0 : BIT;           -- next_state_s0
  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN
  next_state(0) <= (next_state_s2 OR next_state_s5 OR next_state_s6);
  next_state(1) <= (next_state_s1 OR next_state_s4 OR next_state_s5);
  next_state(2) <= (next_state_s0 OR next_state_s1 OR next_state_s5 
OR next_state_s6);
  next_state_s0 <= (current_state_s0 AND NOT(cke));
  current_state_s0 <= (current_state(2) AND NOT(current_state(1)) AND 
NOT(current_state(0)));
  next_state_s1 <= ((current_state_s0 AND cke) OR (current_state_s1 
AND NOT(key_ready)));
  current_state_s1 <= (current_state(2) AND current_state(1) AND NOT(
current_state(0)));
  next_state_s2 <= (current_state_s1 AND key_ready);
  current_state_s2 <= (NOT(current_state(2)) AND current_state(0));
  next_state_s3 <= (current_state_s2 OR (current_state_s3 AND NOT(
finish)));
  current_state_s3 <= (NOT(current_state(2)) AND NOT(current_state(1)) 
AND NOT(current_state(0)));
  next_state_s4 <= (current_state_s3 AND finish);
  current_state_s4 <= (NOT(current_state(2)) AND current_state(1));
  next_state_s5 <= (current_state_s4 OR (current_state_s5 AND NOT(
req_cp)));
  current_state_s5 <= (current_state(1) AND current_state(0));
  next_state_s6 <= ((current_state_s5 AND req_cp) OR 
current_state_s6);
  current_state_s6 <= (current_state(2) AND NOT(current_state(1)) AND 
current_state(0));
  label0 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(0) <= GUARDED (next_state(0) AND NOT(active));
  END BLOCK label0;
  label1 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(1) <= GUARDED (next_state(1) AND NOT(active));
  END BLOCK label1;
  label2 : BLOCK ((NOT((clk'STABLE)) AND NOT(clk)) = '1')
  BEGIN
    current_state(2) <= GUARDED (next_state(2) OR active);
  END BLOCK label2;

sel3(0) <= '0';

sel3(1) <= (active OR (current_state_s0 AND NOT(active)) OR 
(current_state_s1 AND NOT(active)) OR (
current_state_s2 AND NOT(active)) OR (current_state_s3 AND NOT(
active)) OR (current_state_s4 AND NOT(active)) OR (
current_state_s5 AND NOT(active)) OR (current_state_s6 AND NOT(
active)));

sel2(0) <= '0';

sel2(1) <= (active OR (current_state_s0 AND NOT(active)) OR 
(current_state_s1 AND NOT(active)) OR (
current_state_s2 AND NOT(active)) OR (current_state_s3 AND NOT(
active)) OR (current_state_s4 AND NOT(active)) OR (
current_state_s5 AND NOT(active)) OR (current_state_s6 AND NOT(
active)));

sel1(0) <= ((current_state_s2 AND NOT(active)) OR (
current_state_s3 AND NOT(active)) OR (current_state_s4 AND NOT(
active)) OR (current_state_s5 AND NOT(active)) OR (
current_state_s6 AND NOT(active)));

sel1(1) <= (active OR (current_state_s0 AND NOT(active)) OR 
(current_state_s1 AND NOT(active)));

en_out <= (current_state_s3 AND NOT(active) AND finish);

en_rcbc <= '0';

en_iv <= '0';

en_in <= (current_state_s1 AND NOT(active) AND key_ready);

cke_b_mode <= ((current_state_s0 AND NOT(active) AND cke) OR (
current_state_s1 AND NOT(active)) OR (current_state_s2 AND NOT(
active)) OR (current_state_s3 AND NOT(active)) OR (
current_state_s4 AND NOT(active)) OR (current_state_s5 AND NOT(
active)) OR (current_state_s6 AND NOT(active)));

cp_ready <= ((current_state_s4 AND NOT(active)) OR (
current_state_s5 AND NOT(active) AND NOT(req_cp)));

emp_buf <= ((current_state_s2 AND NOT(active)) OR (
current_state_s3 AND NOT(active) AND NOT(finish)));

s_gen_key <= ((current_state_s0 AND NOT(active) AND cke) OR (
current_state_s1 AND NOT(active)) OR (current_state_s2 AND NOT(
active)) OR (current_state_s3 AND NOT(active)) OR (
current_state_s4 AND NOT(active)) OR (current_state_s5 AND NOT(
active)) OR (current_state_s6 AND NOT(active)));

s_mesin <= ((current_state_s2 AND NOT(active)) OR (
current_state_s3 AND NOT(active) AND NOT(finish)));

e_mesin <= ((e AND active) OR (current_state_s0 AND e AND 
NOT(active)) OR (current_state_s1 AND e AND NOT(
active)) OR (current_state_s2 AND e AND NOT(active)) OR
 (current_state_s3 AND e AND NOT(active)) OR (
current_state_s4 AND e AND NOT(active)) OR (current_state_s5 AND 
e AND NOT(active)) OR (current_state_s6 AND e AND 
NOT(active)));
END;