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-- VHDL data flow description generated from `ofb_bop`
--              date : Sat Sep  1 20:21:02 2001


-- Entity Declaration

ENTITY ofb_bop IS
  PORT (
  active : in BIT;      -- active
  clk : in BIT; -- clk
  key_ready : in BIT;   -- key_ready
  dt_ready : in BIT;    -- dt_ready
  finish : in BIT;      -- finish
  first_dt : inout BIT; -- first_dt
  e_mesin : out BIT;    -- e_mesin
  s_mesin : out BIT;    -- s_mesin
  emp_buf : out BIT;    -- emp_buf
  cp_ready : out BIT;   -- cp_ready
  cke_b_mode : out BIT; -- cke_b_mode
  en_in : out BIT;      -- en_in
  en_iv : out BIT;      -- en_iv
  en_rcbc : out BIT;    -- en_rcbc
  en_out : out BIT;     -- en_out
  sel1 : out bit_vector(1 DOWNTO 0) ;   -- sel1
  sel2 : out bit_vector(1 DOWNTO 0) ;   -- sel2
  sel3 : out bit_vector(1 DOWNTO 0) ;   -- sel3
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END ofb_bop;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ofb_bop IS
  SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER;       -- current_state
  SIGNAL aux72 : BIT;           -- aux72
  SIGNAL aux70 : BIT;           -- aux70
  SIGNAL aux66 : BIT;           -- aux66
  SIGNAL aux64 : BIT;           -- aux64
  SIGNAL aux59 : BIT;           -- aux59
  SIGNAL aux57 : BIT;           -- aux57
  SIGNAL aux56 : BIT;           -- aux56
  SIGNAL aux53 : BIT;           -- aux53
  SIGNAL auxinit1 : BIT;                -- auxinit1

BEGIN
  auxinit1 <= (not (active) and not (current_state (2)) and not (current_state
(1)) and (current_state (3) or (current_state (0) and not (aux64))
or aux72));
  aux53 <= (not (active) and current_state (0));
  aux56 <= (not (current_state (0)) and not (active) and not (current_state
(3)) and not (current_state (2)) and not (first_dt) and key_ready
and dt_ready);
  aux57 <= ((not (current_state (1)) or (not (active) and current_state
(3)) or (current_state (2) and aux53)) and (current_state (1)
or (current_state (3) and aux53) or aux56));
  aux59 <= ((not (current_state (2)) and current_state (1) and not (current_state
(3)) and aux53) or (not (current_state (1)) and aux56));
  aux64 <= (not (dt_ready) or not (finish));
  aux66 <= (current_state (1) and not (current_state (2)) and not (current_state
(0)) and not (active));
  aux70 <= (current_state (3) or current_state (0));
  aux72 <= (not (current_state (0)) and key_ready and dt_ready and first_dt);
  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED ((not (active) and current_state (3)) or (not (current_state
(1)) and not (active) and current_state (2)) or aux66 or (not
(current_state (1)) and aux53 and aux64));
  END BLOCK label0;
  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED ((not (current_state (2)) and not (current_state (0)) and current_state
(1)) or not ((not (active) and not ((current_state (3) and current_state
(0))))) or (current_state (2) and current_state (1) and aux70)
or (not (current_state (3)) and not (current_state (2)) and
aux72));
  END BLOCK label1;
  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (2) <= GUARDED (active or (not (current_state (2)) and current_state (3)) or
(current_state (1) and current_state (0)) or (current_state
(3) and current_state (0)) or (not (current_state (1)) and not
(current_state (0)) and current_state (2)) or (not (current_state
(1)) and not (current_state (0)) and not (first_dt) and key_ready
and dt_ready));
  END BLOCK label2;
  label3 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (3) <= GUARDED (not (active) and (not (current_state (2)) or current_state (1))
and aux70 and (current_state (3) or current_state (1) or not
(aux64)));
  END BLOCK label3;

sel3 (0) <= aux57;

sel3 (1) <= not (aux57);

sel2 (0) <= aux59;

sel2 (1) <= not (aux59);

sel1 (0) <= (not (current_state (2)) and not (current_state (0)) and not
(active) and (current_state (1) or (not (current_state (3))
and key_ready and dt_ready and first_dt)));

sel1 (1) <= (active or current_state (2) or (current_state (1) and current_state
(0)) or (not (current_state (3)) and ((current_state (0) and
aux64) or (not (current_state (1)) and not (current_state (0))
and not ((key_ready and dt_ready and first_dt))))));

en_out <= (current_state (2) and current_state (1) and not (current_state
(3)) and aux53);

en_rcbc <= '0';

en_iv <= ((not (current_state (2)) and not (current_state (1)) and not
(active) and current_state (3)) or aux66);

en_in <= auxinit1;

cke_b_mode <= not (active);

cp_ready <= (current_state (3) and current_state (1) and not (current_state
(0)) and not (active));

emp_buf <= auxinit1;

s_mesin <= (not (current_state (1)) and ((current_state (2) and not (active)
and not ((current_state (3) and current_state (0)))) or (not
(current_state (2)) and aux53 and aux64)));

e_mesin <= '1';

first_dt <= not ((not (active) and (aux70 or (current_state (2) xor current_state
(1)))));
END;