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-- VHDL data flow description generated from `reg01`
--              date : Thu Jul 12 08:49:22 2001


-- Entity Declaration

ENTITY reg01 IS
  PORT (
  clk : in BIT; -- clk
  a : in BIT;   -- a
  en : in BIT;  -- en
  clr : in BIT; -- clr
  b : out BIT;  -- b
  vdd : in BIT; -- vdd
  vss : in BIT  -- vss
  );
END reg01;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF reg01 IS
  SIGNAL current_state : REG_VECTOR(1 DOWNTO 0) REGISTER;       -- current_state

BEGIN
  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED (not (clr) and not (current_state (1)) and en);
  END BLOCK label0;
  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED not ((not (clr) and not ((not (current_state (1)) and en))));
  END BLOCK label1;

b <= (not (clr) and a and en and (not (current_state (1)) or not (current_state
(0))));
END;