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-- VHDL data flow description generated from `register`
--              date : Thu Jul  5 15:31:21 2001


-- Entity Declaration

ENTITY register_0 IS
  PORT (
  a : in BIT;   -- a
  clk : in BIT; -- clk
  cke : in BIT; -- cke
  clr : in BIT; -- clr
  en : in BIT;  -- en
  b : out BIT   -- b
  );
END register_0;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF register_0 IS
  SIGNAL current_state : REG_VECTOR(1 DOWNTO 0) REGISTER;       -- current_state

BEGIN
  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (0) <= GUARDED (not (current_state (0)) or not ((not (clr) and not (en))));
  END BLOCK label0;
  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')
  BEGIN
    current_state (1) <= GUARDED (not (current_state (0)) and not (clr) and not (en));
  END BLOCK label1;

b <= (not (current_state (1)) and a and cke and current_state (0)
and not (clr) and not (en));
END;