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-- VHDL data flow description generated from `xor01`
--              date : Sun Jul  1 19:11:34 2001


-- Entity Declaration

ENTITY xor01 IS
  PORT (
  en : in BIT;  -- en
  a : in BIT;   -- a
  b : in BIT;   -- b
  c : out BIT   -- c
  );
END xor01;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF xor01 IS
  SIGNAL rtlalc_0 : REG_BIT REGISTER;   -- rtlalc_0

BEGIN
  label0 : BLOCK (en = '1')
  BEGIN
    rtlalc_0 <= GUARDED (a xor b);
  END BLOCK label0;

c <= rtlalc_0;
END;