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--Nama file : count4x.fsm
--Deskripsi : counter 4 bit
--Author    : Mas Adit
--Tanggal  : 31 Agustus 2001

entity count4x is
port (
        clk : in bit;
        rst : in bit;
       q : out bit_vector(3 downto 0);
       vdd : in bit;
       vss : in bit
      );
end count4x;

architecture STATE_MACHINE of count4x is

type STATE_TYPE IS (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15);

-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE

signal CURRENT_STATE, NEXT_STATE: STATE_TYPE;

begin
  process ( CURRENT_STATE, rst )
    begin
      if ( rst = '1' ) then
          NEXT_STATE <= S0;
          q <= "0000";
      else
          case CURRENT_STATE IS
             when S0 =>
                q <= "0000";
                NEXT_STATE <= S1;
         when S1 =>
                q <= "0001";
                NEXT_STATE <= S2;
             when S2 =>
                q <= "0010";
                NEXT_STATE <= S3;
         when S3 =>
                q <= "0011";
                NEXT_STATE <= S4;
             when S4 =>
                q <= "0100";
                NEXT_STATE <= S5;
             when S5 =>
                q <= "0101";
                NEXT_STATE <= S6;
             when S6 =>
                q <= "0110";
                NEXT_STATE <= S7;
             when S7 =>
                q <= "0111";
                NEXT_STATE <= S8;
             when S8 =>
                q <= "1000";
                NEXT_STATE <= S9;
             when S9 =>
                q <= "1001";
                NEXT_STATE <= S10;
             when S10 =>
                q <= "1010";
                NEXT_STATE <= S11;
         when S11 =>
                q <= "1011";
                NEXT_STATE <= S12;
         when S12 =>
                q <= "1100";
                NEXT_STATE <= S13;
         when S13 =>
                q <= "1101";
                NEXT_STATE <= S14;
             when S14 =>
                q <= "1110";
                NEXT_STATE <= S15;
             when S15 =>
                q <= "1111";
                NEXT_STATE <= S0;
             when OTHERS =>
                assert ( '1' )
                report "Illegal State";

          end case;
      end if;
end process;

process (clk)
  begin
    if ((clk = '1') and not (clk'STABLE)) then
         CURRENT_STATE <= NEXT_STATE;
    end if;
end process;

end STATE_MACHINE;