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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [ctr_enkeyx.fsm] - Rev 9
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--Nama file : ctr_enkeyx.fsm
--Deskripsi : blok kontroller kunci enkripsi
--Author : Mas Adit
--Tanggal : 21 Agustus 2001
entity ctr_enkeyx is
port (
clk : in bit;
rst : in bit;
start : in bit;
count : in bit_vector(2 downto 0);
en_shft : out bit;
en_count : out bit;
sel1 : out bit;
sel2 : out bit;
c_count : out bit;
finish : out bit;
en_out : out bit;
vdd : in bit;
vss : in bit
);
end ctr_enkeyx;
architecture STATE_MACHINE of ctr_enkeyx is
type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10);
--pragma CLOCK clk
--pragma CURRENT_STATE CURRENT_STATE
--pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
process (CURRENT_STATE, rst, start, count)
begin
if rst then
NEXT_STATE <= S0;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '0';
else
case CURRENT_STATE is
when S0 =>
if start then
if (count = "000") then
NEXT_STATE <= S1;
en_shft <= '0';
en_count <= '1';
en_out <= '1';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
else
if (count = "001") then
NEXT_STATE <= S3;
en_shft <= '1';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
else
if (count = "111") then
NEXT_STATE <= S10;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '1';
else
NEXT_STATE <= S6;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '0';
end if;
end if;
end if;
else
NEXT_STATE <= S0;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '0';
end if;
when S1 =>
NEXT_STATE <= S2;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
when S2 =>
NEXT_STATE <= S2;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
when S3 =>
NEXT_STATE <= S4;
en_shft <= '0';
en_count <= '1';
en_out <= '1';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
when S4 =>
NEXT_STATE <= S5;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
when S5 =>
NEXT_STATE <= S5;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
when S6 =>
NEXT_STATE <= S7;
en_shft <= '1';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
when S7 =>
NEXT_STATE <= S8;
en_shft <= '0';
en_count <= '1';
en_out <= '1';
sel1 <= '0';
sel2 <= '1';
c_count <= '0';
finish <= '0';
when S8 =>
NEXT_STATE <= S9;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
when S9 =>
NEXT_STATE <= S9;
en_shft <= '0';
en_count <= '1';
en_out <= '0';
sel1 <= '0';
sel2 <= '1';
c_count <= '1';
finish <= '0';
when S10 =>
NEXT_STATE <= S10;
en_shft <= '0';
en_count <= '0';
en_out <= '0';
sel1 <= '0';
sel2 <= '0';
c_count <= '0';
finish <= '1';
end case;
end if;
end process;
process (clk)
begin
if ((clk = '0') and not(clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
end STATE_MACHINE;