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--Nama file : kontrol_kuncix.fsm
--Deskripsi : kontrol pembangkitan (pengaturan) kunci
--Author    : Mas Adit
--Tanggal  : 24 Agustus 2001

entity kontrol_kuncix is
port (
        clk : in bit;
        start : in bit;
        rst : in bit;
        f_enkey : in bit;
        f_invmul : in bit;
        f_invadd : in bit;
        rst_all : out bit;
        key_ready : out bit;
        s_enkey : out bit;
        s_invmul : out bit;
        s_invadd : out bit;
        vdd : in bit;
        vss : in bit
);
end kontrol_kuncix;

architecture STATE_MACHINE of kontrol_kuncix is

type STATE_TYPE is (S0, S2, S3, S4, S5, S6, S7, S8, S9);
        --pragma CLOCK clk
        --pragma CURRENT_STATE CURRENT_STATE
        --pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;

begin

process (CURRENT_STATE, rst, start, f_enkey, f_invmul, f_invadd)
begin
        if (rst = '1') then
                NEXT_STATE <= S0;
                rst_all <= '1';
                s_enkey <= '0';
                s_invmul <='0';
                key_ready <= '0';
                s_invadd <= '0';
        else


        case CURRENT_STATE is

        when S0 =>
                if (start = '1') then
                        if (f_enkey = '0') then
                                NEXT_STATE <= S3;
                                rst_all <= '0';
                                s_enkey <= '1';
                                s_invmul <='0';
                                key_ready <= '0';
                                s_invadd <= '0';
                        else
                                NEXT_STATE <= S2;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='0';
                                key_ready <= '0';
                                s_invadd <= '0';
                        end if;
                else
                        NEXT_STATE <= S0;
                        rst_all <= '1';
                        s_enkey <= '0';
                        s_invmul <='0';
                        key_ready <= '0';
                        s_invadd <= '0';
                end if;
                when S3 =>
                        NEXT_STATE <= S0;
                        rst_all <= '1';
                        s_enkey <= '0';
                        s_invmul <='0';
                        key_ready <= '0';
                        s_invadd <= '0';
                when S2 =>
                        if (f_invmul = '0') then
                                NEXT_STATE <= S4;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='1';
                                key_ready <= '0';
                                s_invadd <= '0';
                        else
                                NEXT_STATE <= S5;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='0';
                                key_ready <= '0';
                                s_invadd <= '0';
                        end if;
                        when S4 =>
                        if (f_invadd = '0') then
                                NEXT_STATE <= S6;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='1';
                                key_ready <= '0';
                                s_invadd <= '1';
                        else
                                NEXT_STATE <= S7;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='1';
                                key_ready <= '0';
                                s_invadd <= '0';
                        end if;
                        when S5 =>
                        if (f_invadd = '0') then
                                NEXT_STATE <= S8;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='0';
                                key_ready <= '0';
                                s_invadd <= '1';
                        else
                                NEXT_STATE <= S9;
                                rst_all <= '0';
                                s_enkey <= '0';
                                s_invmul <='0';
                                key_ready <= '1';
                                s_invadd <= '0';
                        end if;



                        when S6 =>
                        NEXT_STATE <= S6;
                        rst_all <= '0';
                        s_enkey <= '0';
                        s_invmul <='1';
                        key_ready <= '0';
                        s_invadd <= '1';

                        when S7 =>
                        NEXT_STATE <= S7;
                        rst_all <= '0';
                        s_enkey <= '0';
                        s_invmul <='1';
                        key_ready <= '0';
                        s_invadd <= '0';

                        when S8 =>
                        NEXT_STATE <= S8;
                        rst_all <= '0';
                        s_enkey <= '0';
                        s_invmul <='0';
                        key_ready <= '0';
                        s_invadd <= '1';

                        when S9 =>
                        NEXT_STATE <= S9;
                        rst_all <= '0';
                        s_enkey <= '0';
                        s_invmul <='0';
                        key_ready <= '1';
                        s_invadd <= '0';

        end case;
        end if;
end process;

process (clk)
begin
        if ((clk = '0') and not(clk'STABLE)) then
                CURRENT_STATE <= NEXT_STATE;
        end if;
end process;

end STATE_MACHINE;