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--Nama file : kontrol_utama_invaddx.fsm
--Deskripsi : kontrol utama modul inv_add modulo (2^16 + 1)
--Author    : Mas Adit
--Tanggal  : 28 Agustus 2001

entity kontrol_utama_invaddx is
port (
        clk : in bit;
        rst : in bit;
        start : in bit;
        n_dtin : in bit_vector(4 downto 0);
        n_dtout : in bit_vector(4 downto 0);
        c_cdtin : out bit;
        en_cdtin : out bit;
        c_cdtout : out bit;
        en_cdtout : out bit;
        en_out : out bit;
        en_in : out bit;
        finish : out bit;
        vdd : in bit;
        vss : in bit
);
end kontrol_utama_invaddx;

architecture fsm of kontrol_utama_invaddx is

type STATE_TYPE is (S0, S1, S2, S3, S4);
        --pragma CLOCK clk
        --pragma CURRENT_STATE CURRENT_STATE
        --pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;

begin

process (CURRENT_STATE, rst, start, n_dtout, n_dtin)
begin
        if (rst = '1') then
                NEXT_STATE <= S0;
                en_cdtin <= '0';
                c_cdtin <= '0';
                en_cdtout <= '0';
                c_cdtout <= '0';
                en_in <= '0';
                en_out <= '0';
                finish <= '0';
        else
                case CURRENT_STATE is

                when S0 =>
                if  (start = '1') then
                        if not(n_dtout = "10010") then
                                if (n_dtin = "00000") then
                                        NEXT_STATE <= S1;
                                        en_cdtin <= '1';
                                        c_cdtin <= '0';
                                        en_cdtout <= '1';
                                        c_cdtout <= '0';
                                        en_in <= '1';
                                        en_out <= '0';
                                        finish <= '0';
                                else
                                        NEXT_STATE <= S2;
                                        en_cdtin <= '0';
                                        c_cdtin <= '0';
                                        en_cdtout <= '0';
                                        c_cdtout <= '1';
                                        en_in <= '1';
                                        en_out <= '0';
                                        finish <= '0';
                                end if;
                        else
                                NEXT_STATE <= S4;
                                en_cdtin <= '0';
                                c_cdtin <= '0';
                                en_cdtout <= '0';
                                c_cdtout <= '0';
                                en_in <= '0';
                                en_out <= '0';
                                finish <= '1';
                        end if;
                else
                        NEXT_STATE <= S0;
                        en_cdtin <= '0';
                        c_cdtin <= '0';
                        en_cdtout <= '0';
                        c_cdtout <= '0';
                        en_in <= '0';
                        en_out <= '0';
                        finish <= '0';
                end if;

                when S1 =>
                        NEXT_STATE <= S3;
                        en_cdtin <= '1';
                        c_cdtin <= '1';
                        en_cdtout <= '1';
                        c_cdtout <= '0';
                        en_in <= '0';
                        en_out <= '1';
                        finish <= '0';

                when S2 =>
                        NEXT_STATE <= S3;
                        en_cdtin <= '1';
                        c_cdtin <= '1';
                        en_cdtout <= '1';
                        c_cdtout <= '0';
                        en_in <= '0';
                        en_out <= '1';
                        finish <= '0';

                when S3 =>
                        NEXT_STATE <= S3;
                        en_cdtin <= '1';
                        c_cdtin <= '1';
                        en_cdtout <= '1';
                        c_cdtout <= '0';
                        en_in <= '0';
                        en_out <= '1';
                        finish <= '0';

                when S4 =>
                        NEXT_STATE <= S4;
                        en_cdtin <= '0';
                        c_cdtin <= '0';
                        en_cdtout <= '0';
                        c_cdtout <= '0';
                        en_in <= '0';
                        en_out <= '0';
                        finish <= '1';

                end case;
        end if;
end process;

process (clk)
begin
        if ((clk = '0') and not(clk'STABLE)) then
                CURRENT_STATE <= NEXT_STATE;
        end if;
end process;

end fsm;