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[/] [idea/] [trunk/] [fsm/] [key_regulator/] [kontrol_utama_invmulx.fsm] - Rev 9
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--Nama file : kontrol_utama_invmulx.fsm
--Deskripsi : koontrol utama inv_mul (2^16 + 1)
--Author : Mas Adit
--Tanggal : 26 Agustus 2001
entity kontrol_utama_invmulx is
port (
start : in bit;
clk : in bit;
rst : in bit;
n_stage : in bit_vector( 1 downto 0);
n_iterasi : in bit_vector(3 downto 0);
n_dtin : in bit_vector(4 downto 0);
n_dtout : in bit_vector(4 downto 0);
en_cstage : out bit;
c_cstage : out bit;
en_cite : out bit;
c_cite : out bit;
en_cdtin : out bit;
c_cdtin : out bit;
en_cdtout : out bit;
c_cdtout : out bit;
en_in : out bit;
en_out : out bit;
en_pipe : out bit;
sel : out bit;
finish : out bit;
vdd : in bit;
vss : in bit
);
end kontrol_utama_invmulx;
architecture STATE_MACHINE of kontrol_utama_invmulx is
type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21);
--pragma CLOCK clk
--pragma CURRENT_STATE CURRENT_STATE
--pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
process (CURRENT_STATE, rst, start, n_dtout, n_iterasi, n_stage)
begin
if (rst = '1') then
NEXT_STATE <= S0;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
else
case CURRENT_STATE is
when S0 =>
if (start = '1') then
if not(n_dtout = "10010") then
NEXT_STATE <= S1;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '1';
else
if (n_iterasi = "0000") then
if (n_stage = "00") then
NEXT_STATE <= S2;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S4;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
end if;
else
if (n_iterasi = "1111") then
NEXT_STATE <= S16;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S10;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
end if;
end if;
end if;
else
NEXT_STATE <= S0;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
end if;
when S1 =>
NEXT_STATE <= S1;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '1';
when S2 =>
NEXT_STATE <= S3;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '1';
finish <= '0';
when S3 =>
NEXT_STATE <= S4;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
when S4 =>
if (n_stage = "10") then
NEXT_STATE <= S5;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
else
NEXT_STATE <= S6;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
end if;
when S5 =>
NEXT_STATE <= S7;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
when S6 =>
NEXT_STATE <= S8;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '1';
en_out <= '0';
en_pipe <= '1';
sel <= '1';
finish <= '0';
when S7 =>
NEXT_STATE <= S9;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S8 =>
NEXT_STATE <= S9;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S9 =>
NEXT_STATE <= S9;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '1';
c_cdtin <= '1';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S10 =>
if (n_stage = "10") then
NEXT_STATE <= S11;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S12;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
end if;
when S11 =>
NEXT_STATE <= S13;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
when S12 =>
NEXT_STATE <= S14;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '1';
sel <= '0';
finish <= '0';
when S13 =>
NEXT_STATE <= S15;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S14 =>
NEXT_STATE <= S15;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S15 =>
NEXT_STATE <= S15;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '1';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '1';
c_cdtout <= '0';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S16 =>
if (n_stage = "10") then
NEXT_STATE <= S17;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
else
NEXT_STATE <= S18;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
end if;
when S17 =>
NEXT_STATE <= S19;
en_cstage <= '0';
c_cstage <= '0';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
when S18 =>
NEXT_STATE <= S20;
en_cstage <= '1';
c_cstage <= '0';
en_cite <= '1';
c_cite <= '0';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '0';
en_in <= '0';
en_out <= '1';
en_pipe <= '1';
sel <= '0';
finish <= '0';
when S19 =>
NEXT_STATE <= S21;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S20 =>
NEXT_STATE <= S21;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
when S21 =>
NEXT_STATE <= S21;
en_cstage <= '0';
c_cstage <= '1';
en_cite <= '0';
c_cite <= '1';
en_cdtin <= '0';
c_cdtin <= '0';
en_cdtout <= '0';
c_cdtout <= '1';
en_in <= '0';
en_out <= '0';
en_pipe <= '0';
sel <= '0';
finish <= '0';
end case;
end if;
end process;
process (clk)
begin
if ((clk = '0') and not(clk'STABLE)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
end STATE_MACHINE;