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-- File Name : ofb.fsm
-- Version : v1.2
-- Description : finite state mechine description of ofb mode
-- Purpose : to generate behavioral description of ofb mode
-- Author : Sigit Dewantoro
-- Address : IS Laboratory, Labtek VIII, ITB, Jl. Ganesha 10, Bandung, Indonesia
-- Email : sigit@students.ee.itb.ac.id, sigit@ic.vlsi.itb.ac.id
-- Date : August 23th, 2001
entity ofb is
PORT (
active : in BIT;
clk : in BIT;
key_ready : in BIT;
dt_ready : in BIT;
finish : in BIT;
first_dt : inout BIT;
E_mesin : out BIT;
s_mesin : out BIT;
emp_buf : out BIT;
cp_ready : out BIT;
cke_b_mode : out BIT;
en_in : out BIT;
en_iv : out BIT;
en_rcbc : out BIT;
en_out : out BIT;
sel1 : out BIT_VECTOR (1 downto 0);
sel2 : out BIT_VECTOR (1 downto 0);
sel3 : out BIT_VECTOR (1 downto 0);
vdd : in BIT;
vss : in BIT
);
end ofb;
architecture STATE_MACHINE of ofb is
type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13);
-- pragma CLOCK clk
-- pragma CURRENT_STATE CURRENT_STATE
-- pragma NEXT_STATE NEXT_STATE
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
process (CURRENT_STATE, active, key_ready, dt_ready, first_dt, finish)
begin
if active then
NEXT_STATE <= S0;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '0';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '1';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
else
case CURRENT_STATE is
-- ***********************************************************************
when S0 =>
NEXT_STATE <= S1;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '1';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
-- ***********************************************************************
when S1 =>
if (key_ready and dt_ready) then
if first_dt then
NEXT_STATE <= S2;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '1';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '1';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '1';
sel1 <= "01";
sel2 <= "10";
sel3 <= "10";
else
NEXT_STATE <= S5;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '1';
sel1 <= "10";
sel2 <= "01";
sel3 <= "01";
end if;
else
NEXT_STATE <= S1;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '1';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
end if;
-- ***********************************************************************
when S2 =>
NEXT_STATE <= S3;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '1';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "01";
sel2 <= "10";
sel3 <= "10";
-- ***********************************************************************
when S3 =>
NEXT_STATE <= S4;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "01";
sel3 <= "10";
-- ***********************************************************************
when S4 =>
NEXT_STATE <= S6;
E_mesin <= '1';
s_mesin <= '1';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
-- ***********************************************************************
when S5 =>
NEXT_STATE <= S6;
E_mesin <= '1';
s_mesin <= '1';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
-- ***********************************************************************
when S6 =>
NEXT_STATE <= S7;
E_mesin <= '1';
s_mesin <= '1';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
-- ***********************************************************************
when S7 =>
if (finish and dt_ready) then
NEXT_STATE <= S8;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '1';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '1';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "00";
sel2 <= "10";
sel3 <= "10";
else
NEXT_STATE <= S7;
E_mesin <= '1';
s_mesin <= '1';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "10";
end if;
-- ***********************************************************************
when S8 =>
NEXT_STATE <= S9;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '1';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '1';
en_iv <= '1';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "00";
sel2 <= "10";
sel3 <= "10";
-- ***********************************************************************
when S9 =>
NEXT_STATE <= S10;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "01";
-- ***********************************************************************
when S10 =>
NEXT_STATE <= S11;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '1';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "01";
-- ***********************************************************************
when S11 =>
NEXT_STATE <= S12;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '1';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "01";
-- ***********************************************************************
when S12 =>
NEXT_STATE <= S13;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "01";
-- ***********************************************************************
when S13 =>
NEXT_STATE <= S13;
E_mesin <= '1';
s_mesin <= '0';
emp_buf <= '0';
cp_ready <= '0';
cke_b_mode <= '1';
en_in <= '0';
en_iv <= '0';
en_rcbc <= '0';
en_out <= '0';
first_dt <= '0';
sel1 <= "10";
sel2 <= "10";
sel3 <= "01";
-- ***********************************************************************
end case;
end if;
end process;
process(clk)
begin
if(clk = '0' and not clk' stable) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
end STATE_MACHINE;
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