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-- File Name    : reg01.fsm
-- Description  : finite state mechine description of register 1 bit
-- Author       : Sigit Dewantoro
-- Date         : July 11th, 2001

entity reg01 is
PORT (
        clk             : in BIT;
        a               : in BIT;
        en              : in BIT;
        clr             : in BIT;
        b               : out BIT;
        vdd             : in BIT;
        vss             : in BIT
     );
end reg01;

architecture STATE_MACHINE of reg01 is
        type STATE_TYPE is (S0, S1, S2);

        -- pragma CLOCK clk
        -- pragma CURRENT_STATE CURRENT_STATE
        -- pragma NEXT_STATE NEXT_STATE

        signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;

        begin
        process (CURRENT_STATE, en, clr)
                begin

                if clr then
                        NEXT_STATE <= S0;
                        b <= '0';
                else
                        case CURRENT_STATE is
                        when S0 =>
                        if en then
                                NEXT_STATE <= S1;
                                b <= a;
                        end if;

                        when S1 =>
                        if en then
                                NEXT_STATE <= S2;
                                b <= a;
                        end if;
                        end case;
                end if;
        end process;

        process(clk)
                begin
                if(clk = '0' and not clk'stable) then
                        CURRENT_STATE <= NEXT_STATE;
                end if;
       end process;

end STATE_MACHINE;