Subversion Repositories instruction_list_pipelined_processor_with_peripherals

////////////////////////////////////////////////////////////////////////////////////////////////
////                                                              							////
////                                                              							////
////  	This file is part of the project                 									////
////	"instruction_list_pipelined_processor_with_peripherals"								////
////                                                              							////
////  http://opencores.org/project,instruction_list_pipelined_processor_with_peripherals	////
////                                                              							////
////                                                              							////
//// 				 Author:                                                  				////
////      			- Mahesh Sukhdeo Palve													////
////																						////
////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////
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//// 											                 							////
////                                                              							////
//// 					This source file may be used and distributed without         		////
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//// 					the original copyright notice and the associated disclaimer. 		////
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//// 					This source file is free software; you can redistribute it   		////
//// 					and/or modify it under the terms of the GNU Lesser General   		////
//// 					Public License as published by the Free Software Foundation; 		////
////					either version 2.1 of the License, or (at your option) any   		////
//// 					later version.                                               		////
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//// 					This source is distributed in the hope that it will be       		////
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////////////////////////////////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
`include "defines.v"
 
 
module accumulatorMUX (accMuxSel, immData, aluOut 
								`ifdef timerAndCounter_peripheral
								, tcLoadIn, tcAccIn
								`endif
								`ifdef UART_peripheral
								, uartDataIn, uartStatIn
								`endif
								`ifdef SPI_peripheral
								, spiStatIn, spiBufIn
								`endif
								, accMuxOut
								);
 
	input [`accMuxSelLen-1:0]	accMuxSel;
	input [`immDataLen-1:0]		immData;
	input	[7:0]	aluOut;
	`ifdef timerAndCounter_peripheral
	input [7:0] tcLoadIn, tcAccIn;
	`endif
	`ifdef UART_peripheral
	input [7:0] uartDataIn, uartStatIn;
	`endif
	`ifdef SPI_peripheral
	input [7:0] spiStatIn, spiBufIn;
	`endif
 
	output [7:0]	accMuxOut;
 
	reg [7:0]	accMuxOut;
 
 
	always @ *
	begin
 
		case (accMuxSel)
 
			`accMuxSelImmData	:	begin
										accMuxOut = immData;
										end
 
			`accMuxSelAluOut	:	begin
										accMuxOut = aluOut;
										end
 
			`ifdef timerAndCounter_peripheral
			`accMuxSelTcLoad	:	begin
										accMuxOut = tcLoadIn;
										end
 
			`accMuxSelTcAcc	:	begin
										accMuxOut = tcAccIn;
										end
			`endif
 
			`ifdef UART_peripheral
			`accMuxSelUartData	:		begin
										accMuxOut = uartDataIn;
										end
 
			`accMuxSelUartStat	:		begin
										accMuxOut = uartStatIn;
										end
			`endif
 
			`ifdef SPI_peripheral
			`accMuxSelSpiStat	:	begin
										accMuxOut = spiStatIn;
										end
 
			`accMuxSelSpiBuf	:	begin
										accMuxOut = spiBufIn;
										end
			`endif
 
 
			default		:	begin
								accMuxOut = 8'bzzzzzzzz;
								end
 
		endcase
 
	end
 
 
endmodule