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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [accumulator.v] - Rev 9
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`include "timescale.v" `include "defines.v" module accumulator (accIn, accEn, accOut); input [7:0] accIn; input accEn; output [7:0] accOut; reg [7:0] accOut; always @ (accEn) begin if (accEn) begin accOut = accIn; $write ("\n%b data written to accumulator : module accumulator ", accIn); end else begin accOut = accOut; end end // end always endmodule
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