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[/] [instruction_list_pipelined_processor_with_peripherals/] [trunk/] [hdl/] [bitNegator.v] - Rev 6
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`include "timescale.v" `include "defines.v" module bitNegator (bitIn, bitN, bitOut); input bitIn, bitN; output bitOut; reg bitOut; always @ (bitIn or bitN) begin if (bitN) begin bitOut = ~ bitIn; end else begin bitOut = bitIn; end end endmodule
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