Subversion Repositories integer_square_root

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yihua Liu
// 
// Create Date: 2022/06/08 16:50:36
// Design Name: 
// Module Name: ISR
// Project Name: lab_3_b
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


typedef enum logic [3:0] { 
    INIT,
    GUESS,
    MULT_LOAD,
    MULT_WAIT,
    COMPARE,
    CHANGE,
    CHECK,
    INCRE,
    ENDLOOP,
    DONE
} state;

module ISR_FSM(
    input               reset,
    input        [63:0] value,
    input               clock,
    input               mult_done,
    input        [63:0] mult_result,
    output logic        mult_start,
    output logic        mult_reset,
    output logic [63:0] mult_input,
    output logic [31:0] result,
    output logic        done
);
    
    logic [63:0] value_reg;
    logic [31:0] result_next, guess, guess_next;
    integer i, i_next;

    state current_state, next_state;

    assign mult_input = {32'b0, guess};
    assign mult_start = current_state == MULT_LOAD | current_state == MULT_WAIT;
    assign done = current_state == DONE;
    assign mult_reset = current_state == INIT | current_state == COMPARE;


    always_comb begin
        guess_next = guess;
        i_next = i;
        result_next = result;
        case (current_state)
            INIT: begin
                guess_next = 32'h0000_0000;
                i_next = 31;
                result_next = 0;
                next_state = GUESS;
            end 
            GUESS: begin
                guess_next = guess + (32'h0000_0001 << i);
                next_state = MULT_LOAD;
            end
            MULT_LOAD: next_state = MULT_WAIT;
            MULT_WAIT: next_state = (mult_done) ? COMPARE : MULT_WAIT;
            COMPARE: next_state = (mult_result > value_reg) ? CHANGE : CHECK;
            CHANGE: begin
                guess_next = guess - (32'h0000_0001 << i);
                next_state = CHECK; 
            end
            CHECK: next_state = i ? INCRE : ENDLOOP;
            INCRE: begin
                i_next = i - 1;
                next_state = GUESS;
            end
            ENDLOOP: begin
                result_next = guess;
                next_state = DONE;
            end
            DONE: next_state = DONE;
            default: next_state = INIT;
        endcase
    end

    always_ff @(posedge clock) begin
        if (reset) begin
            current_state <= INIT;
            value_reg <= value;
            result <= 32'b0;
            i <= 31;
            guess <= 32'h0000_0000;
        end
        else begin
            current_state <= next_state;
            value_reg <= value_reg;
            result <= result_next;
            i <= i_next;
            guess <= guess_next;
        end
    end

endmodule



module ISR(
    input               reset,
    input        [63:0] value,
    input               clock,
    output logic [31:0] result,
    output logic        done 
);
    logic mult_start;
    logic mult_done;
    logic [63:0] mult_result;
    logic [63:0] mult_input;
    logic mult_reset;


    mult multiplier(
        .clock(clock),
        .reset(mult_reset),
        .mcand(mult_input),
        .mplier(mult_input),
        .start(mult_start),
        .product(mult_result),
        .done(mult_done)
    );
    
    ISR_FSM FSM(
        .reset(reset),
        .value(value),
        .clock(clock),
        .mult_done(mult_done),
        .mult_result(mult_result),
        .mult_start(mult_start),
        .mult_reset(mult_reset),
        .mult_input(mult_input),
        .result(result),
        .done(done)
    );


endmodule