Subversion Repositories integer_square_root

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Yihua Liu
// 
// Create Date: 2022/06/08 16:50:36
// Design Name: 
// Module Name: ISR
// Project Name: lab_3_b
// Target Devices: xczu7eg-ffvf1517-2-i
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module ISR(
    input               reset,
    input        [63:0] value,
    input               clock,
    output logic [31:0] result,
    output logic        done 
);
    logic [63:0] new_value, proposed_solution_square;
    logic [31:0] proposed_solution;
    logic [4:0] i;
    logic start, it_done, flush;
    logic reset_sync;
    
    mult Multiplier (
        .clock(clock),
        .reset(reset),
        .mcand({32'h00000000, proposed_solution}),
        .mplier({32'h00000000, proposed_solution}),
        .start(start),
        .product(proposed_solution_square),
        .done(it_done)
    );
    
    always_comb begin
//        if (reset_async) begin
//            done = 0;
//            result = 0;
//        end
//        else begin
            // Reduction operator
            // see http://www.asic-world.com/verilog/operators2.html
            // done = ~|i & it_done & ~flush;
            // result[i] = (proposed_solution_square <= new_value) & it_done;
        done = ~|i & it_done & ~flush & ~reset_sync;
        result[i] = (proposed_solution_square <= new_value) & it_done & ~reset_sync;
//        end
    end

    always_ff @(posedge clock or posedge reset) begin
        if (reset) begin
            // done <= 0;
            // result <= 0;
            reset_sync <= 1;
            start <= 0;
            flush <= 0;
            i <= 5'b11111;
            proposed_solution <= 32'h80000000;
            new_value <= value;
        end
        else begin
            reset_sync <= 0;
            start <= !it_done || !flush;
            flush <= it_done;
            // if (!it_done && flush) begin
            //     flush <= 0;
            // end
            if (i && it_done && !flush) begin
                // flush <= 1;
                i <= i - 1;
                proposed_solution[i-1] <= 1;
                proposed_solution[i] <= result[i];
            end
        end
    end
endmodule