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This file contains usage instructions and notes about the Ion CPU core project.
The core structure is briefly explained in sections 1 to 4. The rest of this 
doc describes other aspects of the project: code samples, utility scripts, 
etc.\\
 
This document is not yet a full reference on the Ion core. Instead, it should be 
taken as a companion and commentary to the source code.\\
 
This document assumes you know in some depth the MIPS-I architecture. Terms and
concepts from \cite['See MIPS Run']{see_mips_run} and 
\cite['IDT R3K Reference Manual']{r3k_ref_man} are used throughout the text.\\
 
Last modified: \today
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\chapter{Introduction}
 
\section{Features}
\label{features}
 
This is a MIPS-I compatible CPU, aiming at compatibility with IDT's R3000 
MIPS derivative:\\
 
\begin{framed}
\subsection{Key features}
\begin{enumerate}
    \item Binary compatible to R3000 series of CPUs.\\
        Can use regular R3000 toolchains despite a few unimplemented opcodes 
        listed below.
    \item Kernel/user mode operation as per the architecture definition.
    \item Exception handling compatible to MIPS-I standard.
    \item 4KB direct-mapped code cache.
    \item 4KB direct-mapped, writethrough data cache.
    \item Simplified CP0, mostly compatible to R3000.
    \item All unimplemented opcodes trigger the proper traps.
    \item Includes minimalistic memory handler with interfaces for external 
          SRAM (or FLASH) on 8- and 16-bit data bus.
    \item Size and speed compares favorably to other free MIPS cores.
    \item Fully sinchronous (rising clock edge only). No latches.
    \item Source HDL is vendor independent (Though it has only been tested on 
          Xilinx and Altera synthesis tools).
\end{enumerate}
\end{framed}
 
 
The implementation departs from the standard R3000 in some points:
 
\begin{framed}
\subsection{Non-standard features}
\begin{enumerate}
    \item No MMU and no TLB -- meaning no memory address translation at all.
    \item Cache management simplified in an incompatible way.
    \item A number of R3000 opcodes are unimplemented or implemented in an 
          incompatible way:\\
        Unaligned load/store instructions (formerly patented).\\
        All CPA instructions.\\
        All CP0 instructions related to TLB and the cache.
    \item Some other R3000 CP0 features have been omitted.\\
        This includes the CP0 timer.
    \item Interrupt mask handling simplified in an incompatible way.
\end{enumerate}
\end{framed}
 
Finally, there are some flaws and missing features meant to be fixed in 
subsequent versions:
 
\begin{framed}
\subsection{Missing features to be implemented eventually}
\begin{enumerate}
    \item Hardware interrupts not implemented.
    \item Memory handler does not support dynamic RAM.
    \item Caches are not configurable or parametrizable.
    \item Documentation is disastrously inadequate.
\end{enumerate}
\end{framed}