Subversion Repositories keras_to_fpga

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//// Copyright (C) 2019 Authors and OPENCORES.ORG                 ////
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//////////////////////////////////////////////////////////////////////

module
  axis_mac #(W=32)
  (
    axis_if axis_ay,
    axis_if axis_az,
    output [31:0] result,
    output valid,
    input   aclk,
    input   aresetn
  );

  // --------------------------------------------------------------------
  wire both_valid = axis_ay.tvalid & axis_az.tvalid;
  wire tlast_in = both_valid & axis_ay.tlast & axis_az.tlast;

  // --------------------------------------------------------------------
  enum reg [3:0]
    {
      IDLE        = 4'b0001,
      ACCUMULATE  = 4'b0010,
      FLUSH       = 4'b0100,
      READY       = 4'b1000
    } state, next_state;

  // --------------------------------------------------------------------
  always_ff @(posedge aclk)
    if(~aresetn)
      state <= IDLE;
    else
      state <= next_state;

  // --------------------------------------------------------------------
  always_comb
    case(state)
      IDLE:       if(both_valid)
                    next_state <= ACCUMULATE;
                  else
                    next_state <= IDLE;

      ACCUMULATE: if(tlast_in)
                    next_state <= FLUSH;
                  else
                    next_state <= ACCUMULATE;

      FLUSH:      next_state <= READY;

      READY:      if(both_valid)
                    next_state <= ACCUMULATE;
                  else
                    next_state <= IDLE;

      default:    next_state <= IDLE;
    endcase

  // --------------------------------------------------------------------
  wire accumulate = ((state == ACCUMULATE) & both_valid);
  wire ena = aresetn & (accumulate | (state == FLUSH));
  wire [W-1:0] ay = axis_ay.tdata[W-1:0];
  wire [W-1:0] az = axis_az.tdata[W-1:0];
  wire [1:0] aclr = {~aresetn, ~aresetn | valid};

  mac mac(.clk(aclk), .*);

  // --------------------------------------------------------------------
  assign axis_ay.tready = accumulate;
  assign axis_az.tready = accumulate;
  assign valid = (state == READY);

// --------------------------------------------------------------------
endmodule