URL
https://opencores.org/ocsvn/kvcordic/kvcordic/trunk
Subversion Repositories kvcordic
[/] [kvcordic/] [trunk/] [syn/] [xise/] [log/] [cordic-xst14.6.txt] - Rev 2
Compare with Previous | Blame | View Log
Release 14.6 - xst P.68d (nt)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.-->TABLE OF CONTENTS1) Synthesis Options Summary2) HDL Parsing3) HDL Elaboration4) HDL Synthesis4.1) HDL Synthesis Report5) Advanced HDL Synthesis5.1) Advanced HDL Synthesis Report6) Low Level Synthesis7) Partition Report8) Design Summary8.1) Primitive and Black Box Usage8.2) Device utilization summary8.3) Partition Resource Summary8.4) Timing Report8.4.1) Clock Information8.4.2) Asynchronous Control Signals Information8.4.3) Timing Summary8.4.4) Timing Details8.4.5) Cross Clock Domains Report=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : ".work"Input Format : mixed---- Target ParametersOutput File Name : ".ngc"Output Format : NGCTarget Device : xc6vlx75t-ff484-1---- Source OptionsTop Module Name : cordic---- Target OptionsAdd IO Buffers : no---- General OptionsOptimization Goal : SpeedOptimization Effort : 1==================================================================================================================================================* HDL Parsing *=========================================================================Parsing VHDL file "E:\projects\cordic\sim\rtl_sim\vhdl\operpack.vhd" into library workParsing package <operpack>.Parsing package body <operpack>.Parsing VHDL file "E:\projects\cordic\rtl\vhdl\cordic_cdt_pkg.vhd" into library workParsing package <cordic_cdt_pkg>.Parsing VHDL file "E:\projects\cordic\rtl\vhdl\cordic.vhd" into library workParsing entity <cordic>.Parsing architecture <fsmd> of entity <cordic>.=========================================================================* HDL Elaboration *=========================================================================Elaborating entity <cordic> (architecture <fsmd>) from library <work>.WARNING:HDLCompiler:92 - "E:\projects\cordic\rtl\vhdl\cordic.vhd" Line 367: cordic_hyp_steps should be on the sensitivity list of the processWARNING:HDLCompiler:92 - "E:\projects\cordic\rtl\vhdl\cordic.vhd" Line 387: cordic_tab should be on the sensitivity list of the process=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <cordic>.Related source file is "E:\projects\cordic\rtl\vhdl\cordic.vhd".WARNING:Xst:2999 - Signal 'cordic_hyp_steps', unconnected in block 'cordic', is tied to its initial value.WARNING:Xst:2999 - Signal 'cordic_tab', unconnected in block 'cordic', is tied to its initial value.WARNING:Xst:3035 - Index value(s) does not match array range for signal <cordic_hyp_steps>, simulation mismatch.Found 15x16-bit single-port Read Only RAM <Mram_cordic_hyp_steps> for signal <cordic_hyp_steps>.WARNING:Xst:3035 - Index value(s) does not match array range for signal <cordic_tab>, simulation mismatch.Found 42x16-bit single-port Read Only RAM <Mram_cordic_tab> for signal <cordic_tab>.Found 16-bit register for signal <t5_reg>.Found 16-bit register for signal <x2_reg>.Found 16-bit register for signal <y1_reg>.Found 16-bit register for signal <z2_reg>.Found 16-bit register for signal <k_reg>.Found 16-bit register for signal <zero_reg>.Found 16-bit register for signal <one_reg>.Found 16-bit register for signal <t1_reg>.Found 16-bit register for signal <tabval_reg>.Found 16-bit register for signal <x_reg>.Found 16-bit register for signal <y_reg>.Found 16-bit register for signal <z_reg>.Found 16-bit register for signal <ldirection_reg>.Found 16-bit register for signal <lmode_reg>.Found 16-bit register for signal <t4_reg>.Found 16-bit register for signal <ybyk_reg>.Found 16-bit register for signal <t7_reg>.Found 16-bit register for signal <d_reg>.Found 16-bit register for signal <t0_reg>.Found 16-bit register for signal <offset_reg>.Found 16-bit register for signal <kfinal_reg>.Found 16-bit register for signal <kk_reg>.Found 16-bit register for signal <t9_reg>.Found 16-bit register for signal <t3_reg>.Found 16-bit register for signal <t2_reg>.Found 16-bit register for signal <xbyk_reg>.Found 16-bit register for signal <t6_reg>.Found 16-bit register for signal <t8_reg>.Found 16-bit register for signal <x1_reg>.Found 16-bit register for signal <y2_reg>.Found 16-bit register for signal <z1_reg>.Found 16-bit register for signal <zout>.Found 16-bit register for signal <yout>.Found 16-bit register for signal <xout>.Found 3-bit register for signal <current_state>.Found finite state machine <FSM_0> for signal <current_state>.-----------------------------------------------------------------------| States | 6 || Transitions | 9 || Inputs | 3 || Outputs | 5 || Clock | clk (rising_edge) || Reset | reset (positive) || Reset type | asynchronous || Reset State | s_entry || Power Up State | s_entry || Encoding | auto || Implementation | LUT |-----------------------------------------------------------------------Found 16-bit adder for signal <t2_next[15]_GND_6_o_add_53_OUT> created at line 374.Found 16-bit adder for signal <kk_next[15]_offset_reg[15]_add_63_OUT> created at line 386.Found 16-bit adder for signal <x_reg[15]_ybyk_next[15]_add_72_OUT> created at line 408.Found 16-bit adder for signal <y_reg[15]_xbyk_next[15]_add_73_OUT> created at line 409.Found 16-bit adder for signal <z_reg[15]_tabval_next[15]_add_76_OUT> created at line 412.Found 16-bit adder for signal <k_reg[15]_GND_6_o_add_83_OUT> created at line 428.Found 16-bit subtractor for signal <x_reg[15]_ybyk_next[15]_sub_72_OUT<15:0>> created at line 407.Found 16-bit subtractor for signal <y_reg[15]_xbyk_next[15]_sub_75_OUT<15:0>> created at line 410.Found 16-bit subtractor for signal <z_reg[15]_tabval_next[15]_sub_76_OUT<15:0>> created at line 411.Found 16-bit comparator greater for signal <k_reg[15]_kfinal_reg[15]_LessThan_43_o> created at line 361Found 16-bit comparator greater for signal <k_next[15]_kfinal_reg[15]_LessThan_85_o> created at line 429Summary:inferred 2 RAM(s).inferred 9 Adder/Subtractor(s).inferred 528 D-type flip-flop(s).inferred 2 Comparator(s).inferred 49 Multiplexer(s).inferred 1 Finite State Machine(s).Unit <cordic> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# RAMs : 215x16-bit single-port Read Only RAM : 142x16-bit single-port Read Only RAM : 1# Adders/Subtractors : 916-bit adder : 616-bit subtractor : 3# Registers : 3316-bit register : 33# Comparators : 216-bit comparator greater : 2# Multiplexers : 4916-bit 2-to-1 multiplexer : 49# FSMs : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================WARNING:Xst:2404 - FFs/Latches <one_reg<15:1>> (without init value) have a constant value of 0 in block <cordic>.WARNING:Xst:2404 - FFs/Latches <kfinal_reg<15:4>> (without init value) have a constant value of 0 in block <cordic>.Synthesizing (advanced) Unit <cordic>.INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cordic_hyp_steps> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 15-word x 16-bit | || weA | connected to signal <GND> | high || addrA | connected to signal <k_reg<3:0>> | || diA | connected to signal <GND> | || doA | connected to internal node | |-----------------------------------------------------------------------INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cordic_tab> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.-----------------------------------------------------------------------| ram_type | Distributed | |-----------------------------------------------------------------------| Port A || aspect ratio | 42-word x 16-bit | || weA | connected to signal <GND> | high || addrA | connected to signal <t5_next<5:0>> | || diA | connected to signal <GND> | || doA | connected to internal node | |-----------------------------------------------------------------------Unit <cordic> synthesized (advanced).=========================================================================Advanced HDL Synthesis ReportMacro Statistics# RAMs : 215x16-bit single-port distributed Read Only RAM : 142x16-bit single-port distributed Read Only RAM : 1# Adders/Subtractors : 916-bit adder : 616-bit subtractor : 3# Registers : 501Flip-Flops : 501# Comparators : 216-bit comparator greater : 2# Multiplexers : 4916-bit 2-to-1 multiplexer : 49# FSMs : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================INFO:Xst:2261 - The FF/Latch <kfinal_reg_1> in Unit <cordic> is equivalent to the following 3 FFs/Latches, which will be removed : <kfinal_reg_2> <kfinal_reg_3> <one_reg>Analyzing FSM <MFsm> for best encoding.Optimizing FSM <FSM_0> on signal <current_state[1:3]> with user encoding.-----------------------State | Encoding-----------------------s_entry | 000s_exit | 001s_001_001 | 010s_002_001 | 011s_003_001 | 100s_004_001 | 101-----------------------WARNING:Xst:1710 - FF/Latch <d_reg_15> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_14> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_13> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_12> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_11> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_10> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_9> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_8> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_7> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_6> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_5> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_4> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_3> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_2> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <d_reg_1> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <offset_reg_5> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <offset_reg_0> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <t0_reg_5> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <t0_reg_0> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:2677 - Node <t5_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t5_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t1_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t4_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t0_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t3_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <kk_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t9_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t7_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <offset_reg_15> of sequential type is unconnected in block <cordic>.Optimizing unit <cordic> ...WARNING:Xst:2677 - Node <t6_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t6_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_0> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_1> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_2> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_3> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_4> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_5> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_6> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_7> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_8> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_9> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_10> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_11> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_12> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_13> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_14> of sequential type is unconnected in block <cordic>.WARNING:Xst:2677 - Node <t8_reg_15> of sequential type is unconnected in block <cordic>.WARNING:Xst:1710 - FF/Latch <tabval_reg_15> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <kk_reg_4> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <kk_reg_5> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_4> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_5> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_6> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_7> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_8> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_9> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_10> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_11> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_12> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_13> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_14> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <k_reg_15> (without init value) has a constant value of 0 in block <cordic>. This FF/Latch will be trimmed during the optimization process.INFO:Xst:2261 - The FF/Latch <x2_reg_0> in Unit <cordic> is equivalent to the following FF/Latch, which will be removed : <x1_reg_0>INFO:Xst:2261 - The FF/Latch <z2_reg_0> in Unit <cordic> is equivalent to the following FF/Latch, which will be removed : <z1_reg_0>INFO:Xst:2261 - The FF/Latch <offset_reg_1> in Unit <cordic> is equivalent to the following FF/Latch, which will be removed : <t0_reg_1>INFO:Xst:2261 - The FF/Latch <offset_reg_2> in Unit <cordic> is equivalent to the following FF/Latch, which will be removed : <offset_reg_3>INFO:Xst:2261 - The FF/Latch <t5_reg_0> in Unit <cordic> is equivalent to the following FF/Latch, which will be removed : <kk_reg_0>INFO:Xst:2261 - The FF/Latch <y1_reg_0> in Unit <cordic> is equivalent to the following FF/Latch, which will be removed : <y2_reg_0>INFO:Xst:2261 - The FF/Latch <t0_reg_2> in Unit <cordic> is equivalent to the following 2 FFs/Latches, which will be removed : <t0_reg_3> <kfinal_reg_1>Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 0) on block cordic, actual ratio is 1.FlipFlop current_state_FSM_FFd1 has been replicated 1 time(s)FlipFlop current_state_FSM_FFd3 has been replicated 1 time(s)FlipFlop k_reg_1 has been replicated 1 time(s)Final Macro Processing ...=========================================================================Final Register ReportMacro Statistics# Registers : 310Flip-Flops : 310==================================================================================================================================================* Partition Report *=========================================================================Partition Implementation Status-------------------------------No Partitions were found in this design.-------------------------------=========================================================================* Design Summary *=========================================================================Top Level Output File Name : .ngc.ngcPrimitive and Black Box Usage:------------------------------# BELS : 1046# GND : 1# INV : 1# LUT1 : 4# LUT2 : 17# LUT3 : 28# LUT4 : 149# LUT5 : 69# LUT6 : 527# MUXCY : 113# MUXF7 : 13# VCC : 1# XORCY : 123# FlipFlops/Latches : 310# FDC : 194# FDCE : 116Device utilization summary:---------------------------Selected Device : 6vlx75tff484-1Slice Logic Utilization:Number of Slice Registers: 310 out of 93120 0%Number of Slice LUTs: 795 out of 46560 1%Number used as Logic: 795 out of 46560 1%Slice Logic Distribution:Number of LUT Flip Flop pairs used: 871Number with an unused Flip Flop: 561 out of 871 64%Number with an unused LUT: 76 out of 871 8%Number of fully used LUT-FF pairs: 234 out of 871 26%Number of unique control sets: 4IO Utilization:Number of IOs: 133Number of bonded IOBs: 0 out of 240 0%Specific Feature Utilization:---------------------------Partition Resource Summary:---------------------------No Partitions were found in this design.---------------------------=========================================================================Timing ReportNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORTGENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | NONE(ldirection_reg_0) | 310 |-----------------------------------+------------------------+-------+INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Asynchronous Control Signals Information:----------------------------------------No asynchronous control signals found in this designTiming Summary:---------------Speed Grade: -1Minimum period: 6.273ns (Maximum Frequency: 159.413MHz)Minimum input arrival time before clock: 2.513nsMaximum output required time after clock: 1.256nsMaximum combinational path delay: No path foundTiming Details:---------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'clk'Clock period: 6.273ns (frequency: 159.413MHz)Total number of paths / destination ports: 1871281 / 410-------------------------------------------------------------------------Delay: 6.273ns (Levels of Logic = 23)Source: lmode_reg_4 (FF)Destination: z_reg_15 (FF)Source Clock: clk risingDestination Clock: clk risingData Path: lmode_reg_4 to z_reg_15Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDC:C->Q 2 0.375 0.784 lmode_reg_4 (lmode_reg_4)LUT6:I0->O 7 0.068 0.531 GND_6_o_lmode_reg[15]_equal_60_o<15>11 (GND_6_o_lmode_reg[15]_equal_60_o<15>11)LUT6:I4->O 3 0.068 0.431 n0043<15>1_1 (n0043<15>1)LUT6:I5->O 1 0.068 0.000 Madd_kk_next[15]_offset_reg[15]_add_63_OUT_lut<1> (Madd_kk_next[15]_offset_reg[15]_add_63_OUT_lut<1>)MUXCY:S->O 1 0.290 0.000 Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<1> (Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<1>)MUXCY:CI->O 1 0.020 0.000 Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<2> (Madd_kk_next[15]_offset_reg[15]_add_63_OUT_cy<2>)XORCY:CI->O 20 0.239 0.542 Madd_kk_next[15]_offset_reg[15]_add_63_OUT_xor<3> (kk_next[15]_offset_reg[15]_add_63_OUT<3>)LUT4:I3->O 20 0.068 0.903 Mmux_t5_next101 (t5_next<3>)LUT6:I0->O 3 0.068 0.431 Mmux_tabval_next103 (Mmux_tabval_next102)LUT6:I5->O 1 0.068 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_lut<3> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_lut<3>)MUXCY:S->O 1 0.290 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<3> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<3>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<4> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<4>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<5> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<5>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<6> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<6>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<7> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<7>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<8> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<8>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<9> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<9>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<10> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<10>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<11> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<11>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<12> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<12>)MUXCY:CI->O 1 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<13> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<13>)MUXCY:CI->O 0 0.020 0.000 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<14> (Madd_z_reg[15]_tabval_next[15]_add_76_OUT_cy<14>)XORCY:CI->O 2 0.239 0.497 Madd_z_reg[15]_tabval_next[15]_add_76_OUT_xor<15> (z_reg[15]_tabval_next[15]_add_76_OUT<15>)LUT6:I4->O 1 0.068 0.000 Mmux_z_next71 (z_next<15>)FDCE:D 0.011 z_reg_15----------------------------------------Total 6.273ns (2.154ns logic, 4.119ns route)(34.3% logic, 65.7% route)=========================================================================Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'Total number of paths / destination ports: 619 / 396-------------------------------------------------------------------------Offset: 2.513ns (Levels of Logic = 4)Source: mode<3> (PAD)Destination: offset_reg_4 (FF)Destination Clock: clk risingData Path: mode<3> to offset_reg_4Gate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------LUT5:I4->O 2 0.068 0.784 Mmux_lmode_next101 (lmode_next<3>)LUT6:I0->O 2 0.068 0.644 GND_6_o_lmode_next[15]_equal_37_o<15>11 (GND_6_o_lmode_next[15]_equal_37_o<15>11)LUT6:I2->O 2 0.068 0.784 GND_6_o_lmode_next[15]_equal_39_o<15>1 (GND_6_o_lmode_next[15]_equal_39_o)LUT6:I0->O 1 0.068 0.000 Mmux_t0_next[15]_GND_6_o_mux_39_OUT111 (t0_next[15]_GND_6_o_mux_39_OUT<4>)FDCE:D 0.011 offset_reg_4----------------------------------------Total 2.513ns (0.301ns logic, 2.212ns route)(12.0% logic, 88.0% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'Total number of paths / destination ports: 54 / 50-------------------------------------------------------------------------Offset: 1.256ns (Levels of Logic = 1)Source: current_state_FSM_FFd3 (FF)Destination: ready (PAD)Source Clock: clk risingData Path: current_state_FSM_FFd3 to readyGate NetCell:in->out fanout Delay Delay Logical Name (Net Name)---------------------------------------- ------------FDC:C->Q 395 0.375 0.813 current_state_FSM_FFd3 (current_state_FSM_FFd3)LUT3:I0->O 0 0.068 0.000 current_state__n0432<0>1 (ready)----------------------------------------Total 1.256ns (0.443ns logic, 0.813ns route)(35.3% logic, 64.7% route)=========================================================================Cross Clock Domains Report:--------------------------Clock to Setup on destination clock clk---------------+---------+---------+---------+---------+| Src:Rise| Src:Fall| Src:Rise| Src:Fall|Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|---------------+---------+---------+---------+---------+clk | 6.273| | | |---------------+---------+---------+---------+---------+=========================================================================Total REAL time to Xst completion: 38.00 secsTotal CPU time to Xst completion: 37.57 secs-->Total memory usage is 261536 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 194 ( 0 filtered)Number of infos : 11 ( 0 filtered)