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[/] [lateq/] [trunk/] [hdl_single_type/] [src/] [lateq.vhd] - Rev 3
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------------------------------------------------------------------------------- -- Title : Versatile latency checker/equalizer for pipelines -- Project : ------------------------------------------------------------------------------- -- File : lateq.vhd -- Author : Wojciech M. Zabolotny ( wzab01<at>gmail.com ) -- Company : -- License : BSD -- Created : 2013-11-01 -- Standard : VHDL'93/02 -- Libraries used library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.lateq_pkg.all; use work.ex1_pkg.all; use work.lateq_read_pkg.all; entity lateq is generic ( LEQ_ID : string := "X"; NCHANS : integer := 2 ); port ( -- groups of inputs and outputs din : in T_USER_DATA_SET(0 to NCHANS-1); dout : out T_USER_DATA_SET(0 to NCHANS-1); -- system ports clk : in std_logic; rst_p : in std_logic ); end lateq; architecture beh of lateq is -- declarations -- definition of types and signals used in delay lines type T_DELAY is array (integer range <>) of T_USER_DATA_MRK; signal s_out : T_USER_DATA_SET(0 to NCHANS-1); begin g1 : for i in 0 to NCHANS-1 generate constant NDEL : integer := lateq_read_delays(LEQ_ID, i); signal delay : T_DELAY(0 to NDEL) := (others => C_USER_DATA_MRK_INIT); begin -- signal assignment and processes for delay lines s_out(i) <= delay(0); -- handle the case, where latency is above 0 gp0 : if NDEL > 0 generate pd0 : process(clk, rst_p) is begin if clk'event and clk = '1' then if rst_p = '1' then for i in 0 to NDEL-1 loop delay(i) <= C_USER_DATA_MRK_INIT; end loop; else delay(NDEL-1) <= din(i); for i in 1 to NDEL-1 loop delay(i-1) <= delay(i); end loop; end if; end if; end process pd0; end generate gp0; -- handle the case where latency is 0 (simple copy input to output) gn0 : if NDEL = 0 generate delay(0) <= din(i); end generate gn0; end generate g1; -- Reporting of delays works only in alayzis mode ig1 : if C_LATEQ_MODE = 0 generate --pragma translate off pc1 : process(clk, rst_p) is begin if clk'event and clk = '1' then if rst_p = '1' then null; else for i in 0 to NCHANS-1 loop lateq_report_delay(LEQ_ID, i, din(i).lateq_mrk); end loop; lateq_report_end(LEQ_ID); end if; end if; end process pc1; --pragma translate on end generate ig1; -- Aborting of simulation in final verification mode ig2 : if C_LATEQ_MODE = 1 generate --pragma translate off pc2 : process(clk, rst_p) is variable latm : T_LATEQ_MRK; begin if clk'event and clk = '1' then if rst_p = '1' then null; else latm := s_out(0).lateq_mrk; for i in 1 to NCHANS-1 loop if lateq_mrk_cmp(latm,s_out(i).lateq_mrk) /= 0 then report "ERROR: Inequal latencies in block " & LEQ_ID & " chan 0:" & lateq_mrk_to_str(latm) & " chan " & integer'image(i) & ":" & lateq_mrk_to_str(s_out(i).lateq_mrk) severity FAILURE; end if; end loop; end if; end if; end process pc2; --pragma translate on end generate ig2; -- The process, which assigns outputs pu : process(s_out) is --pragma translate off variable dmin : T_LATEQ_MRK; --pragma translate on begin --pragma translate off dmin := s_out(0).lateq_mrk; --pragma translate on dout <= s_out; --pragma translate off for i in 0 to NCHANS-1 loop if lateq_mrk_cmp(dmin, s_out(i).lateq_mrk) > 0 then dmin := s_out(i).lateq_mrk; end if; end loop; -- now we have found the dmin, so set it in all outputs for i in 0 to NCHANS-1 loop dout(i).lateq_mrk <= dmin; end loop; --pragma translate on end process pu; end beh;
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