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[/] [lateq/] [trunk/] [hdl_various_types/] [src/] [ex1_pkg.vhd] - Rev 3
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------------------------------------------------------------------------------- -- Title : ex1_pkg package -- Project : ------------------------------------------------------------------------------- -- File : ex1_pkg.vhd -- Author : Wojciech M. Zabolotny ( wzab01<at>gmail.com ) -- Company : -- License : BSD -- Created : 2013-11-01 -- Last update: 2015-09-24 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: Package with definitions for the simple system -- demonstrating a method of latency balancing ------------------------------------------------------------------------------- -- Copyright (c) 2015 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2013-11-01 1.0 WZab Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; use IEEE.math_real.all; library work; use work.lateq_pkg.all; package ex1_pkg is -- Constants describing the processor constant C_N_CHANNELS : integer := 64; constant C_DATA_WIDTH : integer := 9; constant C_N_SIDE_CHANS : integer := 3; -- number of neighbouring channels -- Type describing the position of the maximum of the signal subtype T_POS_INT is integer range 0 to C_N_CHANNELS-1; constant C_POS_INT_INIT : T_POS_INT := 0; -- Position of the maximum with time marker type T_POS_INT_MRK is record position : T_POS_INT; -- pragma translate_off lateq_mrk : T_LATEQ_MRK; -- pragma translate_on end record T_POS_INT_MRK; constant C_POS_INT_MRK_INIT : T_POS_INT_MRK := ( -- pragma translate_off lateq_mrk => C_LATEQ_MRK_INIT, -- pragma translate_on position => C_POS_INT_INIT ); -- Data from a single channel subtype T_SINGLE_DATA is signed(C_DATA_WIDTH-1 downto 0); constant C_SINGLE_DATA_INIT : T_SINGLE_DATA := (others => '0'); -- Data from a single channel with time marker,position marker and validity marker type T_SINGLE_DATA_WITH_POS is record -- pragma translate_off lateq_mrk : T_LATEQ_MRK; -- pragma translate_on position : T_POS_INT; valid : boolean; data : T_SINGLE_DATA; end record T_SINGLE_DATA_WITH_POS; constant C_SINGLE_DATA_WITH_POS_INIT : T_SINGLE_DATA_WITH_POS := ( -- pragma translate_off lateq_mrk => C_LATEQ_MRK_INIT, -- pragma translate_on position => C_POS_INT_INIT, valid => false, data => C_SINGLE_DATA_INIT ); -- Function comparing two data with markers function ex1_cmp_data ( constant v1, v2 : T_SINGLE_DATA_WITH_POS) return integer; -- range -1 to 1; -- Vector with all input data type T_INPUT_DATA is array (0 to C_N_CHANNELS-1) of T_SINGLE_DATA; constant C_INPUT_DATA_INIT : T_INPUT_DATA := (others => C_SINGLE_DATA_INIT); -- Record with all input data and time marker - internal form type T_INPUT_DATA_MRK is record -- pragma translate_off lateq_mrk : T_LATEQ_MRK; -- pragma translate_on data_vec : T_INPUT_DATA; end record T_INPUT_DATA_MRK; constant C_INPUT_DATA_MRK_INIT : T_INPUT_DATA_MRK := ( -- pragma translate_off lateq_mrk => C_LATEQ_MRK_INIT, -- pragma translate_on data_vec => (others => C_SINGLE_DATA_INIT) ); -- Here we calculate widths of words needed to store intermadiate calculation -- results. We may assign too many bits. During the synthesis unused bits -- will be optimized out. constant C_CALC_SUM_WIDTH : integer := 2*integer(ceil(log2(real(1+2*C_N_SIDE_CHANS))))+C_DATA_WIDTH; subtype T_CALC_DATA is signed(C_CALC_SUM_WIDTH-1 downto 0); constant C_CALC_DATA_INIT : T_CALC_DATA := (others => '0'); -- Type storing the calculation results with time merker type T_CALC_DATA_MRK is record -- pragma translate_off lateq_mrk : T_LATEQ_MRK; -- pragma translate_on valid : boolean; sum : T_CALC_DATA; end record T_CALC_DATA_MRK; constant C_CALC_DATA_MRK_INIT : T_CALC_DATA_MRK := ( -- pragma translate_off lateq_mrk => C_LATEQ_MRK_INIT, -- pragma translate_on valid => false, sum => C_CALC_DATA_INIT ); -- It would be nice to define the vectors with selected data as follows: -- type T_SEL_DATA_VEC is array (-C_N_SIDE_CHANS to C_N_SIDE_CHANS) of T_SINGLE_DATA; -- Unfortunately it creates problems with other blocks. -- Therefore I must define them with indices starting from 0 -- Vector with selected data type T_SEL_DATA_VEC is array (0 to 2*C_N_SIDE_CHANS) of T_SINGLE_DATA; -- Vector with selected data after calculations type T_CALC_DATA_VEC is array (0 to 2*C_N_SIDE_CHANS) of T_CALC_DATA; -- Vector with selected data and time marker type T_SEL_DATA is record -- pragma translate_off lateq_mrk : T_LATEQ_MRK; -- pragma translate_on data_vec : T_SEL_DATA_VEC; end record T_SEL_DATA; constant C_SEL_DATA_INIT : T_SEL_DATA := ( -- pragma translate_off lateq_mrk => C_LATEQ_MRK_INIT, -- pragma translate_on data_vec => (others => C_SINGLE_DATA_INIT) ); -- Vector with calculation results and time marker type T_CALC_SEL_DATA is record -- pragma translate_off lateq_mrk : T_LATEQ_MRK; -- pragma translate_on data_vec : T_CALC_DATA_VEC; end record T_CALC_SEL_DATA; constant C_CALC_SEL_DATA_INIT : T_CALC_SEL_DATA := ( -- pragma translate_off lateq_mrk => C_LATEQ_MRK_INIT, -- pragma translate_on data_vec => (others => C_CALC_DATA_INIT) ); end package ex1_pkg; package body ex1_pkg is function ex1_cmp_data ( constant v1, v2 : T_SINGLE_DATA_WITH_POS) return integer is begin -- function ex1_cmp_data if v1.data > v2.data then return 1; elsif v2.data > v1.data then return -1; else return 0; end if; end function ex1_cmp_data; end package body ex1_pkg;
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