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[/] [lateq/] [trunk/] [hdl_various_types/] [src/] [lateqgen.py] - Rev 3
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#!/usr/bin/python3 # This file was written by Wojciech M. Zabolotny (wzab@ise.pw.edu.pl) # And is published under BSD license import os import sys import string """ Below we define the entity template, which will be later filled with generated data """ EntTemp=""" ------------------------------------------------------------------------------- -- Title : Latency checker/equalizer for pipelined designs -- Project : ------------------------------------------------------------------------------- -- This file is autmatically generated, please don't -- edit it manually. -- This file is generated by the tool written by Wojciech M. Zabolotny -- ( wzab01<at>gmail.com ) -- This file is licensed under the BSD license -- Libraries used library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; ${packages} entity ${entity_name} is generic ( LEQ_ID : string := "X" ); port ( -- groups of inputs and outputs automatically generated ${ports} -- system ports clk : in std_logic; rst_p : in std_logic ); end ${entity_name}; architecture beh of ${entity_name} is -- declarations -- definition of types and signals used in delay lines ${types_and_dels} begin -- signal assignment and processes for delay lines ${delay_lines} ${delay_check} ${delay_equalize} end beh; """ def type2init(tname): """ This function converts the type name into the name of its initialization constant. Of course it is the user responsibility to define the appropriate types and constants """ tname = tname.upper() if tname[0:2] != "T_": raise(Exception("Wrong type name, should start with T_")) tname="C"+tname[1:]+"_INIT" return tname if len(sys.argv)<4: appname=sys.argv[0] print(string.Template(""" Correct calling syntax: ${appname} entity_name output_file type_0 type_1 type_2 """).substitute(locals())) sys.exit(0) fout=open(sys.argv[2], "w") ndef={} ndef['entity_name']=sys.argv[1] types = sys.argv[3:] ndef['packages']=""" use work.lateq_pkg.all; use work.ex1_pkg.all; use work.lateq_read_pkg.all; """ # Generate ports definition tdef="" for i in range(0, len(types)): tdef += " in"+str(i)+" : in "+types[i]+";\n" tdef += " out"+str(i)+" : out "+types[i]+";\n" ndef['ports'] = tdef # Generate types and signals for delay lines tdef="" for i in range(0, len(types)): tdef += " type TDEL"+str(i)+" is array (integer range <>) of "+types[i]+";\n" tdef += " constant DLEN"+str(i)+" : integer := lateq_read_delays(LEQ_ID,"+str(i)+ ");\n" tdef += " signal s_out"+str(i)+" : "+types[i]+";\n" tdef += " signal del"+str(i)+" : TDEL"+str(i)+"(0 to DLEN"+str(i)+ ") := (others => "+type2init(types[i])+");\n" ndef['types_and_dels'] = tdef # Generate delay lines together with their processes tdef="" for i in range(0, len(types)): # Assign appropriate positions in the delay lines to input and output tdef += " s_out"+str(i)+ "<= del"+str(i)+"(0);\n" # If necessary, generate the process, servicing the delay line tdef += " gp"+str(i)+": if DLEN"+str(i)+" > 0 generate\n" tdef += " pd"+str(i)+" : process(clk,rst_p) is\n" tdef += " begin\n" tdef += " if clk'event and clk='1' then\n" tdef += " if rst_p='1' then\n" tdef += " for i in 0 to DLEN"+str(i)+"-1 loop \n" tdef += " del"+str(i)+"(i) <= "+type2init(types[i])+";\n" tdef += " end loop;\n" tdef += " else\n" tdef += " del"+str(i)+"(DLEN"+str(i)+"-1) <= in"+str(i)+";\n" tdef += " for i in 1 to DLEN"+str(i)+"-1 loop \n" tdef += " del"+str(i)+"(i-1) <= del"+str(i)+"(i);\n" tdef += " end loop;\n" tdef += " end if;\n" tdef += " end if;\n" tdef += " end process pd"+str(i)+";\n" tdef += " end generate gp"+str(i)+";\n" # Generate signal path for case when delay is 0 tdef += " gn"+str(i)+": if DLEN"+str(i)+" = 0 generate\n" tdef += " del"+str(i)+"(0) <= in"+str(i)+";\n" tdef += " end generate gn"+str(i)+";\n" tdef += "\n" ndef['delay_lines'] = tdef # Generate the delay checking and reporting part (only in simulation) tdef="" tdef += " --pragma translate off\n" tdef += " pc : process(clk,rst_p) is\n" tdef += " begin\n" tdef += " if clk'event and clk='1' then\n" tdef += " if rst_p='1' then\n" tdef += " null;\n" tdef += " else\n" tdef += " if C_LATEQ_MODE=0 then\n" tdef += " -- Analyzis mode, report delays\n" for i in range(0,len(types)): tdef += " lateq_report_delay(LEQ_ID,"+str(i)+",in"+str(i)+".lateq_mrk);\n" tdef += " lateq_report_end(LEQ_ID);\n" tdef += " elsif C_LATEQ_MODE=1 then\n" tdef += " -- Final verification mode, assert output latency equality\n" for i in range(1,len(types)): tdef += " if s_out0.lateq_mrk /= s_out"+str(i)+".lateq_mrk then\n" tdef += " report LEQ_ID & \" inequal latencies: out0=\" & \n" tdef += " lateq_mrk_to_str(s_out0.lateq_mrk) & \", out"+str(i)+"=\" &\n" tdef += " lateq_mrk_to_str(s_out"+str(i)+".lateq_mrk) severity FAILURE;\n" tdef += " end if;\n" tdef += " end if;\n" tdef += " end if;\n" tdef += " end if;\n" tdef += " end process pc;\n" tdef += " --pragma translate on\n" ndef['delay_check'] = tdef # Generate the delay adjusting part # Idea is to find the smallest time marker and to propagate it to all outputs. tdef = "" tdef += " pu : process(" for i in range(0, len(types)): if i>0: tdef += ", " tdef += "s_out"+str(i) tdef += ") is\n" tdef += "--pragma translate off\n" tdef += " variable dmin : T_LATEQ_MRK;\n" tdef += "--pragma translate on\n" tdef += " begin\n" for i in range(0, len(types)): tdef += " out"+str(i)+" <= s_out"+str(i)+";\n" tdef += "--pragma translate off\n" # Next part should be performed only for LATEQ_MODE=0 tdef += " if C_LATEQ_MODE=0 then\n" tdef += " dmin := s_out0.lateq_mrk;\n" for i in range(0, len(types)): tdef += " if lateq_mrk_cmp(dmin,s_out"+str(i)+".lateq_mrk) > 0 then\n" tdef += " dmin := s_out"+str(i)+".lateq_mrk;\n" tdef += " end if;\n" tdef += "-- now we have found the dmin, so set it in all outputs\n" for i in range(0, len(types)): tdef += " out"+str(i)+".lateq_mrk <= dmin;\n" tdef += " end if;\n" tdef += "--pragma translate on\n" tdef += " end process pu;\n" ndef['delay_equalize'] = tdef tout=string.Template(EntTemp).substitute(ndef) fout.write(tout) fout.close()
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