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<p align="center"><font face="Times New Roman" size="5">A Little Bit about
Alliance</font></p>
<p align="center"> </p>
<p><font size="4"><b>A. Introduction</b></font></p>
<p><font size="4">Alliance is a Computer Aided Design System for Very Large
Scale Integrated Circuits (VLSI) design. Alliance is a non-commercial
software developed by Équipe Achitecture des Systèmes et Micro-Électronique,
Laboratoire d'Informatique de Paris 6,Université Pierre et Marie Curie,
France. So, if you are interested in Alliance, you can get the software
and more information at <a href="http://www-asim.lip6.fr">http://www-asim.lip6.fr</a>
. We usually run this software under Linux Operating Systems (we use Red
Hat Linux 6.2).</font></p>
<font size="4">The ALLIANCE VHDL</font> is dedicated to digital
synchronous circuits design, which is usually used for:
<ul>
<li><font size="4">logic simulation </font>
<li><font size="4">logic synthesis </font>
<li><font size="4">functional abstraction </font>
<li><font size="4">formal proof</font> </li>
</ul>
<p><font size="4">The ALLIANCE VHDL is fully compatible with the IEEE VHDL
standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE
subset can be simulated with any full-VHDL commercial compiler-simulator.</font></p>
<p><font size="4">The VHDL description of a circuit is made of two separate
parts: the external view and the internal view.</font>
<p><font size="4">The external view defines the name of the circuit and its
interface. The interface of a circuit is a list of ports. Each port is specified
by its name, its mode, its type, its constraint for an array and, its kind.</font>
<p><font size="4">The mode of a port depends only on the manner the port is used
inside the circuit (in the internal view of the circuit). If the value of a port
is to be read in the view of the description, the port must be declared with the
mode <code>IN</code>. If the value of a port is to be written by the internal
view, the port must be declared with the mode <code>OUT</code>. If both above
conditions are satisfied the port must be declared with the mode <code>INOUT</code>.</font>
<font size="4">Only structural and behavioural data flow are supported as
internal view.</font>
<p><font size="4">A circuit, a subcircuit, or a cell can have two different
descriptions:</font>
<ul>
<li><font size="4">a structural view may be defined in a file with a <code>.vst</code>
extension </font>
<li><font size="4">a behavioural data flow description may be defined in a
file with a <code>.vbe</code> extension.</font></li>
</ul>
<p> </p>
<p><font size="4"><b>B. Starting Using Alliance</b></font></p>
<p><font size="4">We can start using Alliance by linking our workspace to the
source of Alliance by typing :</font></p>
<p> <font size="4">
<b>source /home/cad/alliance/share/etc/alc_env.csh</b></font></p>
<p><font size="4">here we assume that the Alliance is located in directory
/home/cad.</font></p>
<p><font size="4">The next step is to set the environment of Alliance. We
usually use logic gates from <b>sclib</b> to develop a circuit. So, we
must set the environment by typing :<br>
</font></p>
<p> <font size="4"><b>setenv
MBK_CATA_LIB .:/home/cad/alliance/archi/Linux/cells/sclib</b></font></p>
<p><font size="4">We must know the symbolic name of gate that we use by seeing
manual of <b>sclib</b>. To see manual of all about command we want to know, we
can type </font></p>
<p> <font size="4">
<b>man name_of_command </b></font></p>
<p><font size="4">After that, we can start our design by typing the source code
in the text editor. Our design can be from behavioural data flow
description or logic circuit description. We can write our comment like
this :</font></p>
<p> <font size="4">
/* our_comment */</font></p>
<p><font size="4">If our design comes from behavioural data flow description, we
save it with a <b>.vbe</b> extension. You can see examples of
behavioural D-Flip Flop design <a href="dflipflop.shtml">here</a>. </font></p>
<p><font size="4">If our design comes from logic circuit description, we save it
with a <b>.c</b> extension.</font> <font size="4">In
order to write this file, we must follow the syntax below :</font></p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>genlib.h is required for all genlib programs.<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>it defines the set of functions we will use for schematic capture<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/</p>
<p>#include <genlib.h><br>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>decoder.c is to become the `core' executable program. So we must<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>define a main procedure main()<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/<o:p>
</o:p>
</p>
<p>main()<br>
{<br>
DEF_LOFIG("decoder"); /* decoder.c is our file
name */<br>
</p>
<p style="margin: 0">/* define inputs and outputs of our system */</p>
<p class="MsoNormal" style="margin: 0"> </p>
<p class="MsoNormal" style="margin: 0">/*<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin: 0"><span style="mso-spacerun: yes">
</span>We start with the input terminals.<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin: 0"><span style="mso-spacerun: yes">
</span>Only signals and connectors can be vectorized.<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin: 0">*/<o:p>
</o:p>
</p>
<p style="word-spacing: 0; margin: 0">LOCON("x", IN, "x" );
/* define input */<br>
LOCON("res", IN, "res" );
/* define reset input, if we need it */<br>
LOCON("ck", IN, "ck" );
/* define clock input */</p>
<p style="word-spacing: 0; margin: 0">LOCON("z", INOUT, "z"
); /* define an output of a gate
but acts as input of another gate */</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>Then,<span style="mso-spacerun: yes"> </span>the output terminals.<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/<o:p>
</o:p>
</p>
<p style="word-spacing: 0; margin: 0"><br>
LOCON("y[0:1]", OUT, "y[0:1]" );
/* define output consists of 2
bits*/</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0"> </p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">/*<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>Then the supplies.<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>They are inputs, but we like them better at the end of the<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>description.<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">*/<o:p>
</o:p>
</p>
<p style="word-spacing: 0; margin: 0">LOCON("vdd", IN, "vdd"
); /* define vdd input */<br>
LOCON("vss", IN, "vss" );
/* define vss input */<br>
<br>
....</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0">/* define all components that we use to
develop our system */</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0">LOINS("a2_y", "a1",
"x", "m", "z", "vdd", "vss",0);</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0">/* a2_y is a simbolic name for 2
inputs <b>and gate</b> */</p>
<p style="word-spacing: 0; margin: 0">/*<b> </b>a1 is our given name for
this component where there must be no same name in<b> </b>the same file */</p>
<p style="word-spacing: 0; margin: 0">/* x and m is inputs of a1 */</p>
<p style="word-spacing: 0; margin: 0">/* z is the output of a1 */</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0">....</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">SAVE_LOFIG();<o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0"><span style="mso-spacerun: yes">
</span>exit(0);<span style="mso-spacerun: yes">
</span>/* necessary for the proper run of the Makefile */ <o:p>
</o:p>
</p>
<p class="MsoNormal" style="margin-top: 0; margin-bottom: 0">}<span style="mso-spacerun: yes">
</span><o:p>
</o:p>
</p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0"><font size="4"><a href="counter.shtml">Here</a>
we can see the example <b>.c</b> file of 4-bit counter.</font></p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0"><font size="4"><b>C. Basic Alliance
Tools</b></font></p>
<p style="word-spacing: 0; margin: 0"> </p>
<p style="word-spacing: 0; margin: 0"><font size="4">After that, we </font><font size="4">are
now ready to actually design the chip and use the Alliance tools. The design
flow for this little example is composed of 5 main steps:</font></p>
<ul>
<li>
<p style="margin-top: 0; margin-bottom: 0"><font size="4">behavioral capture
and simulation</font></li>
<li>
<p style="margin-top: 0; margin-bottom: 0"><font size="4">netlist capture
and validation</font></li>
<li>
<p style="margin-top: 0; margin-bottom: 0"><font size="4">physical layout
generation</font></li>
<li>
<p style="margin-top: 0; margin-bottom: 0"><font size="4">design validation</font></li>
<li>
<p style="margin-top: 0; margin-bottom: 0"><font size="4">symbolic to real
conversion.</font></li>
</ul>
<p><font size="4">First of all, we must make a structural file (<b>.vst</b>).
We can get structural view from our behavioural data flow description (<b>.vbe</b>)
file or from our <b>.c</b> file. Here are the basic Alliance tools :</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(i)<span style="mso-spacerun: yes">
</span>genlib</font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">By
using this tool, we can change our logic circuit description file (<b>.c</b>)
into structural file (<b>.vst</b>) which more useful in next process. <b><O:P>
</b>The command is :</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">
<b> </b>
<b>genlib .c_file_name</O:P>
</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(ii)<span style="mso-spacerun: yes">
</span>scmap<O:P>
</font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
behavioural data flow description file (<b>.vbe</b>) can be changed into
structural file (<b>.vst</b>) by using this tool. The command is :<br>
</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4"><b>
scmap .vbe_ file_name .vst_file_name
</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">We
can see the structural file (<b>.vst</b>) generated from the previous
behavioural D-Flip Flop design <a href="struct.shtml">here</a>.<b></O:P>
</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(iii)
asimut </font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">This
tool is usually used to simulate our design by giving some inputs. We can
see simulation results, which can be compared to our expected outputs. We
must create a test pattern file (<b>.pat</b>) contains some inputs we will
use in the simulation. You can see the example of test pattern file <a href="test.shtml">here</a>.
The command is :</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4"><br>
<b> asimut .vst_file_name test_pattern_file_name
simulation_results_file_name</b> <b><O:P>
</O:P>
</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(iv)
xsch<O:P>
</O:P>
</font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">We
can see logic circuit of our structural file by using this tools.</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(v)
xpat<O:P>
</O:P>
</font></b></p>
<font size="4">We can see timing diagrams of test pattern file (<b>.pat</b>) and our asimut
result file (<b>.pat</b>) by using <b>xpat</b> tool.</font>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(vi)
scr<O:P>
</O:P>
</font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
structural file can be extracted into symbolic layout using <b>scr</b>.
The command is :<br>
<b>scr -sclib -p -r file_name</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">This
symbolic layout result (<b>.ap</b>) can be viewed by <b>graal</b> tool.<b><O:P>
</O:P>
</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(vii)
s2r</font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
symbolic layout can be changed into real layout by using <b>s2r</b>. The
command is :<br>
<b>
s2r file_name</b> </font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">This
real layout (<b>.cif</b>) can be viewed by using <b>dreal</b> tool.</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><b><font size="4">(viii) <span style="mso-spacerun: yes">
</span>lynx<O:P>
</O:P>
</font></b></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">Our
real layout can be changed into new structural file (<b>.al</b>) by using <b>lynx</b>.
First, we must set the environmet by the command :</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4"><b> </b>
<b>setenv MBK_OUT_LO al</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">then
we type the command :</font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"> <font size="4">
<b>lynx -v .ap_file_name output_file_name -f</b></font></p>
<p class="MsoNormal" style="LINE-HEIGHT: 150%; TEXT-ALIGN: justify"><font size="4">After
this, we can do simulation post-layout on the old (<b>.vst</b>) and new (<b>.al</b>)
structural file by using <b>lvx</b>. The command is : </font></p>
<p><b><font size="4">
lvx vst al .vst_file_name .al_file_name</font></b></p>
<p><font size="4">Another way to compare the result is using <b>asimut</b>.
We can simulate the new structural file (<b>.al</b>) with the previous test
pattern file using asimut. But first, we must set the environment :<br>
</font></p>
<p><b> </b><font size="4"><b>
setenv MBK_IN_LO al</b></font></p>
<p><font size="4">then using <b>asimut</b> :</font></p>
<p align="center"><font size="4"><b>
asimut .al_file_name testpattern_file_name result_file_name </b></font></p>
<p><font size="4">After that we can compare the new simulation result with the
previous simulation result. We expect to get the same result.</font></p>
<p> </p>
<p><font size="4">To know more about Alliance and find tutorials, you can
visit <a href="http://www-asim.lip6.fr">http://www-asim.lip6.fr</a></font></p>
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