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<html> <head> <title>OPENCORES.ORG</title> <META NAME="keywords" CONTENT="cores, VHDL, Verilog HDL, ASIC, Synthesizable, standard cell, IP, Intellectual Property, 32-bit RISC, UART, PCI, SDRAM, full custom, system on a chip, SOC, reusable, design, development, synthesis, designs, developers, C, Linux, eCos, open, free, open source cores, RTL code, system-on-a-chip, circuits, digital, GNU, GPL, core, controller, processor, system design, chip design, EDA, design methodology, design tools, ASICs, programmable logic, FPGA's, PLDs, CPLDs, verification, Synthesis, HDL, Simulation, IC design software, semiconductor design, integrated circuits, system designs, chip designs, EDAs, design methodologies, design tool, ASIC, programmable logics, FPGA, PLD, CPLD, Synthesis, circuit, Synopsys, system design, chip design, programmable logic, FPGA's, PLDs, CPLDs, verification, Simulation"> <META NAME="description" CONTENT="OPENCORES.ORG endorses development and hosts a repository of free, open source IP cores (chip designs, System-on-a-Chip) and supplemental boards."> </head> <body bgcolor=#ffffff> <table width="100%" cellspacing=5 cellpadding=0 border=0> <tr valign="top"><td> <center> <table cellspacing=0 cellpadding=5 width="100%" valign="top" border=0> <tr valign="top"><td bgcolor=#f0f0f0 valign="top"> <center><font size=+3><b>OPENCORES.ORG</b></font> <br><font size=-4><font color=#ffffff>.</font></font> <br> </center> </td></tr></table> </center> </td></tr> <tr valign="top"><td> <table border=0 cellspacing=0 cellpadding=5 width="100%"><tr valign="top"><td bgcolor="#f8f8f0"> </td> <td valign="top"> <table cellpadding=5><tr><td valign="top"> <font SIZE="2">-- File Name : dffres.vbe -- <p>-- Modul Name : Standar Cell for D Flip-flop using Reset --</p> <p>-- Purpose : To be used by SCMAP --</p> <p>-- Author : Martadinata A --</p> <p>-- Date : 14 November 2000 --</p> <p>ENTITY dffres IS</p> <p>PORT (</p> <p>input : in bit;</p> <p>clk : in bit;</p> <p>reset : in bit;</p> <p>output : out bit;</p> <p>vdd : in bit;</p> <p>vss : in bit</p> <p>);</p> <p>END dffres;</p> <p>ARCHITECTURE VBE OF dffres IS</p> <p>SIGNAL dffres_reg : REG_BIT REGISTER;</p> <p> </p> <p>BEGIN</p> <p>ASSERT ((vdd and not (vss)) = '1')</p> <p>REPORT "power supply is missing on dffres"</p> <p>SEVERITY WARNING;</p> <p> </p> <p> </p> <p>dff : BLOCK ( ( clk AND NOT (clk'STABLE)) = '1' )</p> <p>BEGIN</p> <p>dffres_reg <= GUARDED '1' WHEN (reset = '1') else NOT input;</p> <p>END BLOCK dff;</p> <p> </p> <p>output <= NOT dffres_reg ;</p> <p>END ;</p> </font> <b><font size=+1>Maintainers and Authors :</font></b> <p>LCD Driver development team <p>current members: <ul> <li> <a href="mailto:marta@vlsi.itb.ac.id">Hendra Gunawan</a></li> <li> <a href="mailto:sigit@students.ee.itb.ac.id">Nurhadi Wiyono</a></li> <li> <a href="mailto:sigit@students.ee.itb.ac.id">Kharisma Sinung P</a></li> </ul> <p> <b><font size=+1>Mailing-list:</font></b> <ul><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a></ul> </td></tr></table> </td></tr> <tr><td bgcolor="#f8f8f0"> </td> <td valign="bottom"> <table cellspacing=0 cellpadding=4 border=0 width="100%"bgcolor="#f0f0f0"><tr> <td align=left><i><small>Last modified on Sunday, 17-Sep-2000 03:58:04 JAVT</i></td> <td align=right><i><small>Copyright © 1999-2000 OPENCORES.ORG. All rights reserved.</td> </tr></table> </td></tr></table> </td></tr></table> </body></html>