Subversion Repositories lcd_block

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      <outfile xil_pn:name="top_hw_testbench_map.map"/>
      <outfile xil_pn:name="top_hw_testbench_map.mrp"/>
      <outfile xil_pn:name="top_hw_testbench_map.ncd"/>
      <outfile xil_pn:name="top_hw_testbench_map.ngm"/>
      <outfile xil_pn:name="top_hw_testbench_map.xrpt"/>
      <outfile xil_pn:name="top_hw_testbench_summary.xml"/>
      <outfile xil_pn:name="top_hw_testbench_usage.xml"/>
    </transform>
    <transform xil_pn:end_ts="1337877971" xil_pn:in_ck="6001200367856259123" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="-5563652517805085498" xil_pn:start_ts="1337877946">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
      <outfile xil_pn:name="top_hw_testbench.ncd"/>
      <outfile xil_pn:name="top_hw_testbench.pad"/>
      <outfile xil_pn:name="top_hw_testbench.par"/>
      <outfile xil_pn:name="top_hw_testbench.ptwx"/>
      <outfile xil_pn:name="top_hw_testbench.unroutes"/>
      <outfile xil_pn:name="top_hw_testbench.xpi"/>
      <outfile xil_pn:name="top_hw_testbench_pad.csv"/>
      <outfile xil_pn:name="top_hw_testbench_pad.txt"/>
      <outfile xil_pn:name="top_hw_testbench_par.xrpt"/>
    </transform>
    <transform xil_pn:end_ts="1337877998" xil_pn:in_ck="5725138416503842291" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="287829442711806529" xil_pn:start_ts="1337877971">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
      <outfile xil_pn:name="top_hw_testbench.bgn"/>
      <outfile xil_pn:name="top_hw_testbench.bit"/>
      <outfile xil_pn:name="top_hw_testbench.drc"/>
      <outfile xil_pn:name="top_hw_testbench.ut"/>
      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
    </transform>
    <transform xil_pn:end_ts="1337878052" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="5582947192412673156" xil_pn:start_ts="1337878050">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1337878222" xil_pn:in_ck="5725138416503829437" xil_pn:name="TRAN_analyzeDesignUsingChipscope" xil_pn:prop_ck="-7079812952058613934" xil_pn:start_ts="1337878222">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
    <transform xil_pn:end_ts="1337877971" xil_pn:in_ck="-7080687810229386346" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416186" xil_pn:start_ts="1337877968">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
      <outfile xil_pn:name="top_hw_testbench.twr"/>
      <outfile xil_pn:name="top_hw_testbench.twx"/>
    </transform>
  </transforms>

</generated_project>