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Subversion Repositories lcd_block
[/] [lcd_block/] [trunk/] [hdl/] [iseProject/] [iseProject.xise] - Rev 16
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xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/><property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/><property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/><property xil_pn:name="Report Paths by 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xil_pn:valueState="default"/><property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/><property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/><property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/><property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/><property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/><property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/><property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/><property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/><property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/><property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/><property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/><property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/><!-- --><!-- The following properties are for internal use only. These should not be modified.--><!-- --><property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|testLcd_controller" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DesignName" xil_pn:value="iseProject" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/><property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/><property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/><property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-19T02:48:31" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9ED1F6C9CD464D97A1D4037501F78EBA" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/><property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/></properties><bindings><binding xil_pn:location="/top_hw_testbench" xil_pn:name="pins_hw_testbench.ucf"/></bindings><libraries/><autoManagedFiles><!-- The following files are identified by `include statements in verilog --><!-- source files and are automatically managed by Project Navigator. --><!-- --><!-- Do not hand-edit this section, as it will be overwritten when the --><!-- project is analyzed based on files automatically identified as --><!-- include files. --></autoManagedFiles></project>
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