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Some possible changes/enhancements:

The address register for indirect load/stores could be made
permanent and visible. One could reuse the loaded contents
for several DM accesses (e.g. local variables on the stack).
Would need an additional register and a MUX selecting from
that register or forwarding the just read address from the
DM.

If not implementing this address register, the combination
of load address and load/store should be implemented as
a pseudo instruction in the assembler to avoid programming
errors:
        load (Rx+n)
        store (Rx+n)

The content of A could also be written into DM in the next
cycle. This would extend the pipeline to three stages. But
it would be a funny mix between a register architecture and
an accumulator architecture, where the result is written
into two places (A and Rx). Would safe a store sometimes.

        A + Rx -> A, Ry