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[/] [leros/] [trunk/] [vhdl/] [altera/] [cyc_pll.vhd] - Rev 3
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-- -- -- This file is a part of JOP, the Java Optimized Processor -- -- Copyright (C) 2001-2008, Martin Schoeberl (martin@jopdesign.com) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- as generated by the wizzard and added generic LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; ENTITY pll IS generic (multiply_by : natural; divide_by : natural); PORT ( inclk0 : IN STD_LOGIC := '0'; c0 : OUT STD_LOGIC ); END pll; ARCHITECTURE SYN OF pll IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; SIGNAL sub_wire2 : STD_LOGIC ; SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0); SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0); COMPONENT altpll GENERIC ( clk0_duty_cycle : NATURAL; lpm_type : STRING; clk0_multiply_by : NATURAL; inclk0_input_frequency : NATURAL; clk0_divide_by : NATURAL; pll_type : STRING; clk0_time_delay : STRING; intended_device_family : STRING; operation_mode : STRING; compensate_clock : STRING; clk0_phase_shift : STRING ); PORT ( inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire4_bv(0 DOWNTO 0) <= "0"; sub_wire4 <= To_stdlogicvector(sub_wire4_bv); sub_wire1 <= sub_wire0(0); c0 <= sub_wire1; sub_wire2 <= inclk0; sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2; altpll_component : altpll GENERIC MAP ( clk0_duty_cycle => 50, lpm_type => "altpll", clk0_multiply_by => multiply_by, inclk0_input_frequency => 50000, -- 20MHz = 50000ps clk0_divide_by => divide_by, pll_type => "AUTO", clk0_time_delay => "0", intended_device_family => "Cyclone", operation_mode => "NORMAL", compensate_clock => "CLK0", clk0_phase_shift => "0" ) PORT MAP ( inclk => sub_wire3, clk => sub_wire0 ); END SYN;