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[/] [leros/] [trunk/] [vhdl/] [xilinx/] [sp3epll.vhd] - Rev 4
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-------------------------------------------------------------------------------- -- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 12.4 -- \ \ Application : xaw2vhdl -- / / Filename : sp3epll.vhd -- /___/ /\ Timestamp : 03/07/2011 17:03:15 -- \ \ / \ -- \___\/\___\ -- --Command: xaw2vhdl-st X:\\leros\xilinx\nexys2\ipcore_dir\.\sp3epll.xaw X:\\leros\xilinx\nexys2\ipcore_dir\.\sp3epll --Design Name: sp3epll --Device: xc3s500e-4fg320 -- -- Module sp3epll -- Generated by Xilinx Architecture Wizard -- Written for synthesis tool: XST -- Period Jitter (unit interval) for block DCM_SP_INST = 0.14 UI -- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.70 ns library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity sp3epll is generic ( multiply_by : integer; divide_by : integer); port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic); end sp3epll; architecture BEHAVIORAL of sp3epll is signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT <= '0'; CLKIN_IBUFG_OUT <= CLKIN_IBUFG; CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLKIN_IBUFG_INST : IBUFG port map (I=>CLKIN_IN, O=>CLKIN_IBUFG); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_SP_INST : DCM_SP generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => divide_by, CLKFX_MULTIPLY => multiply_by, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 20.000, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"C080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>RST_IN, CLKDV=>open, CLKFX=>CLKFX_BUF, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>open, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>LOCKED_OUT, PSDONE=>open, STATUS=>open); end BEHAVIORAL;
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