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[/] [light8080/] [trunk/] [sw/] [tb/] [tb1/] [tb1.lst] - Rev 74
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0001 0000 ;*******************************************************************************0002 0000 ; tb1.asm -- light8080 core test bench 1: interrupt & halt test0003 0000 ;*******************************************************************************0004 0000 ; Should be used with test bench template vhdl\test\tb_template.vhdl0005 0000 ; Assembler format compatible with TASM for DOS and Linux.0006 0000 ;*******************************************************************************0007 0000 ; This program will test a few different interrupt vectors and the interrupt0008 0000 ; enable/disable flag, but not exhaustively.0009 0000 ; Besides, it will not test long intr assertions (more than 1 cycle).0010 0000 ;*******************************************************************************0011 00000012 0000 ; DS pseudo-directive; reserve space in bytes, without initializing it0013 0000 #define ds(n) \.org $+n0014 00000015 0000 ; OUTing some value here will trigger intr in the n-th cycle from the end of0016 0000 ; the 'out' instruction. For example, writing a 0 will trigger intr in the 1st0017 0000 ; cycle of the following instruction, and so on.0018 0000 intr_trigger: .equ 11h0019 0000 ; The value OUTput to this address will be used as the 'interrupt source' when0020 0000 ; the intr line is asserted. In the inta acknowledge cycle, the simulated0021 0000 ; interrupt logic will feed the CPU the instruction at memory address0022 0000 ; 40h+source*4. See vhdl\test\tb_template.vhdl for details.0023 0000 intr_source: .equ 10h0024 0000 ; The value OUTput to this port is the number of cycles the intr signal will0025 0000 ; remain high after being asserted. By default this is 1 cycle.0026 0000 intr_width: .equ 12h0027 0000 ; OUTing something here will stop the simulation. A 0x055 will signal a0028 0000 ; success, a 0x0aa a failure.0029 0000 test_outcome: .equ 20h0030 00000031 0000 ;*******************************************************************************0032 00000033 0000 .org 0H0034 0000 C3 60 00 jmp start ; skip the rst address area0035 00030036 0003 ; used to test that RST works0037 0020 .org 20H0038 0020 C6 01 adi 1H0039 0022 FB ei0040 0023 C9 ret0041 00240042 0024 ; used to test the RST instruction as intr vector0043 0028 .org 28H0044 0028 3C inr a0045 0029 FB ei0046 002A C9 ret0047 002B0048 002B ;***** simulated interrupt vectors in area 0040h-005fh *****************0049 002B0050 0040 .org 40h+(0*4) ; simulated interrupt vector 00051 0040 3C inr a0052 0044 .org 40h+(1*4) ; simulated interrupt vector 10053 0044 EF rst 50054 0048 .org 40h+(2*4) ; simulated interrupt vector 20055 0048 23 inx h0056 004C .org 40h+(3*4) ; simulated interrupt vector 30057 004C 3E 42 mvi a,42h0058 0050 .org 40h+(4*4) ; simulated interrupt vector 40059 0050 21 34 12 lxi h,1234h0060 0054 .org 40h+(5*4) ; simulated interrupt vector 50061 0054 C3 2F 01 jmp test_jump0062 0058 .org 40h+(6*4) ; simulated interrupt vector 60063 0058 CD 34 01 call test_call0064 005C .org 40h+(7*4) ; simulated interrupt vector 70065 005C CD 37 01 call shouldnt_trigger0066 005F0067 005F0068 005F ;***** program entry point *********************************************0069 005F0070 0060 start: .org 60H0071 0060 31 7A 01 lxi sp,stack0072 00630073 0063 ; first of all, make sure the RST instruction works, we have a valid0074 0063 ; simulated stack, etc.0075 0063 3E 13 mvi a,13h0076 0065 E7 rst 4 ; this should add 1 to ACC0077 0066 FE 14 cpi 14h0078 0068 C2 2A 01 jnz fail0079 006B0080 006B ; now we'll try a few different interrupt vectors (single byte and0081 006B ; multi-byte). Since interrupts are disabled upon acknowledge, we have0082 006B ; to reenable them after every test.0083 006B0084 006B ; try single-byte interrupt vector: INR A0085 006B 3E 00 mvi a,00086 006D D3 10 out intr_source0087 006F FB ei0088 0070 3E 14 mvi a,014h0089 0072 D3 11 out intr_trigger0090 0074 3E 27 mvi a,027h0091 0076 00 nop ; the interrupt will hit in this nop area0092 0077 00 nop0093 0078 00 nop0094 0079 00 nop0095 007A FE 28 cpi 028h0096 007C C2 2A 01 jnz fail0097 007F0098 007F ; another single-byte vector: RST 50099 007F 3E 01 mvi a,10100 0081 D3 10 out intr_source0101 0083 FB ei0102 0084 3E 14 mvi a,014h0103 0086 D3 11 out intr_trigger ; the interrupt vector will do a rst 5, and0104 0088 3E 20 mvi a,020h ; the rst routine will add 1 to the ACC0105 008A 00 nop ; and reenable interrupts0106 008B 00 nop0107 008C 00 nop0108 008D 00 nop0109 008E FE 21 cpi 021h0110 0090 C2 2A 01 jnz fail0111 00930112 0093 ; another single-byte code: INX H0113 0093 21 FF 13 lxi h,13ffh0114 0096 3E 02 mvi a,20115 0098 D3 10 out intr_source0116 009A FB ei0117 009B 3E 04 mvi a,40118 009D D3 11 out intr_trigger0119 009F 00 nop0120 00A0 00 nop0121 00A1 7D mov a,l0122 00A2 FE 00 cpi 0H0123 00A4 C2 2A 01 jnz fail0124 00A7 7C mov a,h0125 00A8 FE 14 cpi 14h0126 00AA C2 2A 01 jnz fail0127 00AD0128 00AD ; a two-byte instruction: mvi a, 42h0129 00AD 3E 03 mvi a,30130 00AF D3 10 out intr_source0131 00B1 FB ei0132 00B2 3E 04 mvi a,40133 00B4 D3 11 out intr_trigger0134 00B6 00 nop0135 00B7 00 nop0136 00B8 FE 42 cpi 42h0137 00BA C2 2A 01 jnz fail0138 00BD0139 00BD ; a three-byte instruction: lxi h,1234h0140 00BD 3E 04 mvi a,40141 00BF D3 10 out intr_source0142 00C1 FB ei0143 00C2 3E 04 mvi a,40144 00C4 D3 11 out intr_trigger0145 00C6 00 nop0146 00C7 00 nop0147 00C8 7C mov a,h0148 00C9 FE 12 cpi 12h0149 00CB C2 2A 01 jnz fail0150 00CE 7D mov a,l0151 00CF FE 34 cpi 34h0152 00D1 C2 2A 01 jnz fail0153 00D40154 00D4 ; a 3-byte jump: jmp test_jump0155 00D4 ; if this fails, the test will probably derail0156 00D4 3E 05 mvi a,50157 00D6 D3 10 out intr_source0158 00D8 FB ei0159 00D9 3E 04 mvi a,40160 00DB D3 11 out intr_trigger0161 00DD 00 nop0162 00DE 00 nop0163 00DF comeback:0164 00DF FE 79 cpi 79h0165 00E1 C2 2A 01 jnz fail0166 00E40167 00E4 ; a 3-byte call: call test_call0168 00E4 ; if this fails, the test will probably derail0169 00E4 3E 06 mvi a,60170 00E6 D3 10 out intr_source0171 00E8 FB ei0172 00E9 3E 04 mvi a,40173 00EB D3 11 out intr_trigger0174 00ED 3C inr a0175 00EE ; the interrupt will come back here, hopefully0176 00EE 00 nop0177 00EF FE 05 cpi 05h0178 00F1 C2 2A 01 jnz fail0179 00F4 78 mov a,b0180 00F5 FE 19 cpi 19h0181 00F7 C2 2A 01 jnz fail0182 00FA0183 00FA ; now, with interrupts disabled, make sure interrupts are ignored0184 00FA F3 di0185 00FB 3E 07 mvi a,07h ; source 7 catches any unwanted interrupts0186 00FD D3 10 out intr_source0187 00FF 3E 04 mvi a,04h0188 0101 D3 11 out intr_trigger0189 0103 00 nop0190 0104 00 nop0191 0105 00 nop0192 01060193 0106 ; Ok. So far we have tested only 1-cycle intr assertions. Now we'll0194 0106 ; see what happens when we leave intr asserted for a long time (as would0195 0106 ; happen intr was used for single-step debugging, for instance)0196 01060197 0106 ; try single-byte interrupt vector (INR A)0198 0106 3E 50 mvi a, 800199 0108 D3 12 out intr_width0200 010A 3E 01 mvi a,10201 010C D3 10 out intr_source0202 010E FB ei0203 010F 3E 14 mvi a,014h0204 0111 D3 11 out intr_trigger0205 0113 3E 27 mvi a,027h0206 0115 00 nop ; the interrupts will hit in this nop area0207 0116 00 nop0208 0117 3C inr a0209 0118 00 nop0210 0119 00 nop0211 011A 3C inr a0212 011B 00 nop0213 011C 00 nop0214 011D 00 nop0215 011E 00 nop0216 011F 00 nop0217 0120 FE 2B cpi 02bh0218 0122 C2 2A 01 jnz fail0219 01250220 01250221 0125 ; finished, run into the success outcome code0222 01250223 0125 success:0224 0125 3E 55 mvi a,55h0225 0127 D3 20 out test_outcome0226 0129 76 hlt0227 012A 3E AA fail: mvi a,0aah0228 012C D3 20 out test_outcome0229 012E 76 hlt0230 012F0231 012F test_jump:0232 012F 3E 79 mvi a,79h0233 0131 C3 DF 00 jmp comeback0234 01340235 0134 test_call:0236 0134 06 19 mvi b,19h0237 0136 C9 ret0238 01370239 0137 ; called when an interrupt has been acknowledged that shouldn't have0240 0137 shouldnt_trigger:0241 0137 C3 2A 01 jmp fail0242 013A0243 013A ; data space0244 013A ds(64)0244 017A0245 017A stack: ds(2)0245 017C0246 017C .end0247 017C tasm: Number of errors = 0