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Fitter report for LBSun Jan 10 21:12:59 2010Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version---------------------; Table of Contents ;---------------------1. Legal Notice2. Fitter Summary3. Fitter Settings4. HardCopy II Device Resource Guide5. Pin-Out File6. Fitter Resource Usage Summary7. Input Pins8. Output Pins9. I/O Bank Usage10. All Package Pins11. Output Pin Default Load For Reported TCO12. Fitter Resource Utilization by Entity13. Delay Chain Summary14. Pad To Core Delay Chain Fanout15. Control Signals16. Global & Other Fast Signals17. Non-Global High Fan-Out Signals18. Fitter RAM Summary19. Interconnect Usage Summary20. LAB Logic Elements21. LAB-wide Signals22. LAB Signals Sourced23. LAB Signals Sourced Out24. LAB Distinct Inputs25. I/O Rules Summary26. I/O Rules Details27. I/O Rules Matrix28. Fitter Device Options29. Operating Settings and Conditions30. Fitter Messages31. Fitter Suppressed Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2007 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------------+; Fitter Summary ;+-------------------------------+-----------------------------------------------+; Fitter Status ; Successful - Sun Jan 10 21:12:58 2010 ;; Quartus II Version ; 7.2 Build 207 03/18/2008 SP 3 SJ Full Version ;; Revision Name ; LB ;; Top-level Entity Name ; LB ;; Family ; Stratix II ;; Device ; EP2S15F484C3 ;; Timing Models ; Final ;; Logic utilization ; 8 % ;; Combinational ALUTs ; 524 / 12,480 ( 4 % ) ;; Dedicated logic registers ; 870 / 12,480 ( 7 % ) ;; Total registers ; 870 ;; Total pins ; 145 / 343 ( 42 % ) ;; Total virtual pins ; 0 ;; Total block memory bits ; 154,560 / 419,328 ( 37 % ) ;; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;; Total PLLs ; 0 / 6 ( 0 % ) ;; Total DLLs ; 0 / 2 ( 0 % ) ;+-------------------------------+-----------------------------------------------++-----------------------------------------------------------------------------------------------------------------------------------------+; Fitter Settings ;+-----------------------------------------------------------------------+--------------------------------+--------------------------------+; Option ; Setting ; Default Value ;+-----------------------------------------------------------------------+--------------------------------+--------------------------------+; Device ; AUTO ; ;; Fit Attempts to Skip ; 0 ; 0.0 ;; Use smart compilation ; Off ; Off ;; Maximum processors allowed for parallel compilation ; 1 ; 1 ;; Use TimeQuest Timing Analyzer ; Off ; Off ;; Router Timing Optimization Level ; Normal ; Normal ;; Placement Effort Multiplier ; 1.0 ; 1.0 ;; Router Effort Multiplier ; 1.0 ; 1.0 ;; Always Enable Input Buffers ; Off ; Off ;; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;; Optimize Fast-Corner Timing ; Off ; Off ;; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;; Optimize Timing ; Normal compilation ; Normal compilation ;; Optimize IOC Register Placement for Timing ; On ; On ;; Limit to One Fitting Attempt ; Off ; Off ;; Final Placement Optimizations ; Automatically ; Automatically ;; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;; Fitter Initial Placement Seed ; 1 ; 1 ;; PCI I/O ; Off ; Off ;; Weak Pull-Up Resistor ; Off ; Off ;; Enable Bus-Hold Circuitry ; Off ; Off ;; Auto Global Memory Control Signals ; Off ; Off ;; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto ; Auto ;; Auto Delay Chains ; On ; On ;; Auto Merge PLLs ; On ; On ;; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;; Perform Register Duplication for Performance ; Off ; Off ;; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;; Perform Register Retiming for Performance ; Off ; Off ;; Perform Asynchronous Signal Pipelining ; Off ; Off ;; Fitter Effort ; Auto Fit ; Auto Fit ;; Physical Synthesis Effort Level ; Normal ; Normal ;; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;; Auto Register Duplication ; Auto ; Auto ;; Auto Global Clock ; On ; On ;; Auto Global Register Control Signals ; On ; On ;; Stop After Congestion Map Generation ; Off ; Off ;; Save Intermediate Fitting Results ; Off ; Off ;+-----------------------------------------------------------------------+--------------------------------+--------------------------------+Color Legend:-- Green:-- Package Resource: The HardCopy II device package can be migrated from the selected Stratix II device package, and the design has been fitted with the target device migration enabled.-- Other Device Resources: The resource quantity is within the acceptable range of the HardCopy II device and package, indicating that migration from the selected Stratix II device package will likely be successful. You must compile and check the HardCopy II companion revision to ensure migration is successful.-- Orange:-- Package Resource: The HardCopy II device package can be migrated from the selected Stratix II device package; however, the design has not been fitted with the target device migration enabled.-- Other Device Resources: The resource quantity is within the acceptable range of the HardCopy II device and package; however, the resource is constrained so much that the design may not migrate.-- Red:-- Package Resource: The HardCopy II device package cannot be migrated from the selected Stratix II device package.-- Other Device Resources: The design did not migrate because the resource quantity exceeds the acceptable range of the HardCopy II device and package, or, for other reasons detailed in the footnotes.Note: The used resource quantities listed for each HardCopy II device and package combination are estimates only.Migrate your design from the selected Stratix II device and compile for the HardCopy II companion revision to obtain the most accurate measurement of HardCopy II resource utilization.Note: The Device Resource Guide cannot estimate the routing demand by the design in a HardCopy II device.Migrate your design from the selected Stratix II device and compile for the HardCopy II companion revision to confirm routability of the design in the selected HardCopy II device.+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+; HardCopy II Device Resource Guide ;+-----------------------------------+----------------------+--------------+--------------+--------------+--------------+---------------+---------------+---------------+; Resource ; Stratix II EP2S15 ; HC210W ; HC210 ; HC220 ; HC220 ; HC230 ; HC240 ; HC240 ;+-----------------------------------+----------------------+--------------+--------------+--------------+--------------+---------------+---------------+---------------+; Migration Compatibility ; ; None ; None ; None ; None ; None ; None ; None ;; Primary Migration Constraint ; ; Package ; Package ; Package ; Package ; Package ; Package ; Package ;; Package* ; FBGA - 484 ; FBGA - 484 ; FBGA - 484 ; FBGA - 672 ; FBGA - 780 ; FBGA - 1020 ; FBGA - 1020 ; FBGA - 1508 ;; Logic ; -- ; 2% ; 2% ; 1% ; 1% ; 1% ; 1% ; 1% ;; -- Logic cells ; 1023 ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; -- DSP elements ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;; Pins ; ; ; ; ; ; ; ; ;; -- Total ; 145 ; 145 / 309 ; 145 / 335 ; 145 / 493 ; 145 / 495 ; 145 / 699 ; 145 / 743 ; 145 / 952 ;; -- Differential Input ; 0 ; 0 / 66 ; 0 / 70 ; 0 / 90 ; 0 / 90 ; 0 / 128 ; 0 / 224 ; 0 / 272 ;; -- Differential Output ; 0 ; 0 / 44 ; 0 / 50 ; 0 / 70 ; 0 / 70 ; 0 / 112 ; 0 / 200 ; 0 / 256 ;; -- PCI / PCI-X ; 0 ; 0 / 159 ; 0 / 166 ; 0 / 244 ; 0 / 246 ; 0 / 358 ; 0 / 366 ; 0 / 471 ;; -- DQ ; 0 ; 0 / 20 ; 0 / 20 ; 0 / 50 ; 0 / 50 ; 0 / 204 ; 0 / 204 ; 0 / 204 ;; -- DQS ; 0 ; 0 / 8 ; 0 / 8 ; 0 / 18 ; 0 / 18 ; 0 / 72 ; 0 / 72 ; 0 / 72 ;; Memory ; ; ; ; ; ; ; ; ;; -- M-RAM ; 0 ; 0 / 0 ; 0 / 0 ; 0 / 2 ; 0 / 2 ; 0 / 6 ; 0 / 9 ; 0 / 9 ;; -- M4K blocks & M512 blocks** ; 42 ; 42 / 190 ; 42 / 190 ; 42 / 408 ; 42 / 408 ; 42 / 614 ; 42 / 816 ; 42 / 816 ;; PLLs ; ; ; ; ; ; ; ; ;; -- Enhanced ; 0 ; 0 / 2 ; 0 / 2 ; 0 / 2 ; 0 / 2 ; 0 / 4 ; 0 / 4 ; 0 / 4 ;; -- Fast ; 0 ; 0 / 2 ; 0 / 2 ; 0 / 2 ; 0 / 2 ; 0 / 4 ; 0 / 8 ; 0 / 8 ;; DLLs ; 0 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 2 ; 0 / 2 ; 0 / 2 ;; SERDES ; ; ; ; ; ; ; ; ;; -- RX ; 0 ; 0 / 17 ; 0 / 21 ; 0 / 31 ; 0 / 31 ; 0 / 46 ; 0 / 92 ; 0 / 116 ;; -- TX ; 0 ; 0 / 18 ; 0 / 19 ; 0 / 29 ; 0 / 29 ; 0 / 44 ; 0 / 88 ; 0 / 116 ;; Configuration ; ; ; ; ; ; ; ; ;; -- CRC ; 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ;; -- ASMI ; 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ;; -- Remote Update ; 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ; 0 / 0 ;; -- JTAG ; 0 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ; 0 / 1 ;+-----------------------------------+----------------------+--------------+--------------+--------------+--------------+---------------+---------------+---------------+* The selected Stratix II device cannot migrate to any HardCopy II device, regardless of the design. Try this design with a different Stratix II device.** Design contains one or more M512 blocks, which cannot be migrated to HardCopy II devices.+--------------+; Pin-Out File ;+--------------+The pin-out file can be found in C:/Documents and Settings/Shadi/Desktop/LB/LB.pin.+---------------------------------------------------------------------------+; Fitter Resource Usage Summary ;+----------------------------------------------+----------------------------+; Resource ; Usage ;+----------------------------------------------+----------------------------+; ALUTs Used ; 524 / 12,480 ( 4 % ) ;; Dedicated logic registers ; 870 / 12,480 ( 7 % ) ;; ; ;; ALUTs Unavailable ; 10 ;; -- Due to unpartnered 7 input function ; 1 ;; -- Due to unpartnered 6 input function ; 9 ;; ; ;; Combinational ALUT usage by number of inputs ; ;; -- 7 input functions ; 1 ;; -- 6 input functions ; 42 ;; -- 5 input functions ; 67 ;; -- 4 input functions ; 135 ;; -- <=3 input functions ; 279 ;; ; ;; Combinational ALUTs by mode ; ;; -- normal mode ; 327 ;; -- extended LUT mode ; 1 ;; -- arithmetic mode ; 196 ;; -- shared arithmetic mode ; 0 ;; ; ;; Logic utilization ; 1,023 / 12,480 ( 8 % ) ;; -- ALUT/register pairs used ; 1013 ;; -- Combinational with no register ; 143 ;; -- Register only ; 489 ;; -- Combinational with a register ; 381 ;; -- ALUT/register pairs unavailable ; 10 ;; ; ;; Total registers* ; 870 / 14,410 ( 6 % ) ;; -- Dedicated logic registers ; 870 / 12,480 ( 7 % ) ;; -- I/O registers ; 0 / 1,930 ( 0 % ) ;; ; ;; ALMs: partially or completely used ; 524 / 6,240 ( 8 % ) ;; ; ;; Total LABs: partially or completely used ; 77 / 780 ( 10 % ) ;; ; ;; User inserted logic elements ; 0 ;; Virtual pins ; 0 ;; I/O pins ; 145 / 343 ( 42 % ) ;; -- Clock pins ; 16 / 16 ( 100 % ) ;; Global signals ; 2 ;; M512s ; 3 / 104 ( 3 % ) ;; M4Ks ; 39 / 78 ( 50 % ) ;; Total block memory bits ; 154,560 / 419,328 ( 37 % ) ;; Total block memory implementation bits ; 181,440 / 419,328 ( 43 % ) ;; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;; PLLs ; 0 / 6 ( 0 % ) ;; Global clocks ; 2 / 16 ( 13 % ) ;; Regional clocks ; 0 / 32 ( 0 % ) ;; SERDES transmitters ; 0 / 38 ( 0 % ) ;; SERDES receivers ; 0 / 42 ( 0 % ) ;; Average interconnect usage ; 4% ;; Peak interconnect usage ; 10% ;; Maximum fan-out node ; clk~clkctrl ;; Maximum fan-out ; 912 ;; Highest non-global fan-out signal ; reset ;; Highest non-global fan-out ; 213 ;; Total fan-out ; 6070 ;; Average fan-out ; 3.07 ;+----------------------------------------------+----------------------------+* Register count does not include registers inside block RAM or DSP blocks.+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Input Pins ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+; clk ; N20 ; 1 ; 0 ; 10 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[0] ; AB6 ; 7 ; 30 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[1] ; V2 ; 6 ; 40 ; 3 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[2] ; Y6 ; 7 ; 31 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[3] ; R7 ; 6 ; 40 ; 3 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[4] ; T10 ; 7 ; 30 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[5] ; V1 ; 6 ; 40 ; 3 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[6] ; Y8 ; 7 ; 29 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_ctrl[7] ; AA5 ; 7 ; 31 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[0] ; B9 ; 9 ; 26 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[10] ; K8 ; 5 ; 40 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[11] ; L15 ; 2 ; 0 ; 17 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[12] ; B8 ; 4 ; 26 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[13] ; C9 ; 9 ; 26 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[14] ; L8 ; 5 ; 40 ; 17 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[15] ; A8 ; 4 ; 26 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[16] ; N1 ; 6 ; 40 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[17] ; R4 ; 6 ; 40 ; 6 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[18] ; W9 ; 10 ; 26 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[19] ; N3 ; 6 ; 40 ; 10 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[1] ; A7 ; 4 ; 29 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[20] ; P3 ; 6 ; 40 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[21] ; R3 ; 6 ; 40 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[22] ; AA7 ; 7 ; 29 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[23] ; A6 ; 4 ; 30 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[24] ; T1 ; 6 ; 40 ; 7 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[25] ; K4 ; 5 ; 40 ; 18 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[26] ; N4 ; 6 ; 40 ; 10 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[27] ; N2 ; 6 ; 40 ; 10 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[28] ; P6 ; 6 ; 40 ; 8 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[29] ; N19 ; 1 ; 0 ; 10 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[2] ; C8 ; 4 ; 29 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[30] ; K20 ; 2 ; 0 ; 18 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[31] ; K19 ; 2 ; 0 ; 18 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[32] ; B11 ; 4 ; 22 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[33] ; A10 ; 9 ; 25 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[34] ; J3 ; 5 ; 40 ; 19 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[35] ; L3 ; 5 ; 40 ; 16 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[36] ; L21 ; 2 ; 0 ; 16 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[37] ; C12 ; 4 ; 22 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[38] ; M2 ; 5 ; 40 ; 16 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[39] ; M3 ; 5 ; 40 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[3] ; N8 ; 6 ; 40 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[40] ; D10 ; 9 ; 25 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[41] ; C10 ; 9 ; 25 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[42] ; C11 ; 4 ; 22 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[43] ; B12 ; 4 ; 22 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[44] ; L20 ; 2 ; 0 ; 16 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[45] ; B15 ; 3 ; 14 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[46] ; M20 ; 2 ; 0 ; 16 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[47] ; H12 ; 3 ; 15 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[48] ; C15 ; 3 ; 14 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[49] ; D11 ; 3 ; 15 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[4] ; AA8 ; 7 ; 26 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[50] ; A15 ; 3 ; 14 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[51] ; C16 ; 3 ; 14 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[52] ; E12 ; 3 ; 15 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[53] ; U12 ; 8 ; 15 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[54] ; L16 ; 2 ; 0 ; 17 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[55] ; A13 ; 3 ; 18 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[56] ; K22 ; 2 ; 0 ; 17 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[57] ; L7 ; 5 ; 40 ; 17 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[58] ; G12 ; 3 ; 17 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[59] ; H11 ; 3 ; 17 ; 27 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[5] ; C7 ; 4 ; 29 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[60] ; K2 ; 5 ; 40 ; 17 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[61] ; B13 ; 3 ; 18 ; 27 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[62] ; K3 ; 5 ; 40 ; 18 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[63] ; K15 ; 2 ; 0 ; 18 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[6] ; Y9 ; 10 ; 25 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[7] ; N22 ; 1 ; 0 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[8] ; D13 ; 3 ; 18 ; 27 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_data[9] ; K21 ; 2 ; 0 ; 17 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[0] ; D18 ; 3 ; 1 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[1] ; C5 ; 4 ; 31 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[2] ; W16 ; 8 ; 5 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[3] ; E16 ; 3 ; 2 ; 27 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[4] ; F6 ; 4 ; 38 ; 27 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[5] ; D20 ; 3 ; 3 ; 27 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[6] ; F1 ; 5 ; 40 ; 23 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[7] ; V16 ; 8 ; 2 ; 0 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[8] ; U19 ; 1 ; 0 ; 4 ; 3 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_key[9] ; V19 ; 1 ; 0 ; 3 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_rd ; B7 ; 4 ; 29 ; 27 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; in_wr ; Y7 ; 7 ; 29 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; out_rdy ; U6 ; 7 ; 37 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;; reset ; M21 ; 2 ; 0 ; 16 ; 2 ; 214 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ;+-------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Output Pins ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+; in_rdy ; H19 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[0] ; Y5 ; 7 ; 31 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[10] ; P17 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[11] ; AA12 ; 8 ; 18 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[12] ; AB15 ; 8 ; 14 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[13] ; Y15 ; 8 ; 14 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[14] ; P18 ; 1 ; 0 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[15] ; AA15 ; 8 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[16] ; N21 ; 1 ; 0 ; 10 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[17] ; AB13 ; 8 ; 18 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[18] ; V11 ; 8 ; 17 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[19] ; AA11 ; 7 ; 22 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[1] ; AB5 ; 7 ; 31 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[20] ; W11 ; 8 ; 17 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[21] ; P19 ; 1 ; 0 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[22] ; V9 ; 10 ; 26 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[23] ; Y13 ; 8 ; 15 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[24] ; P8 ; 6 ; 40 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[25] ; K1 ; 5 ; 40 ; 17 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[26] ; AB10 ; 10 ; 25 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[27] ; P7 ; 6 ; 40 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[28] ; Y10 ; 7 ; 22 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[29] ; P2 ; 6 ; 40 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[2] ; L2 ; 5 ; 40 ; 16 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[30] ; T2 ; 6 ; 40 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[31] ; AA9 ; 10 ; 25 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[32] ; W10 ; 7 ; 22 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[33] ; K7 ; 5 ; 40 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[34] ; AA10 ; 10 ; 25 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[35] ; N7 ; 6 ; 40 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[36] ; AB8 ; 7 ; 26 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[37] ; R21 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[38] ; P21 ; 1 ; 0 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[39] ; W13 ; 8 ; 15 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[3] ; B5 ; 4 ; 31 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[40] ; R6 ; 6 ; 40 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[41] ; P16 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[42] ; N16 ; 1 ; 0 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[43] ; N15 ; 1 ; 0 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[44] ; C13 ; 3 ; 18 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[45] ; AA13 ; 8 ; 18 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[46] ; P20 ; 1 ; 0 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[47] ; Y12 ; 8 ; 18 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[4] ; R2 ; 6 ; 40 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[5] ; R22 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_mac[6] ; W12 ; 8 ; 17 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[7] ; V12 ; 8 ; 17 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[8] ; E11 ; 3 ; 17 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_mac[9] ; Y11 ; 7 ; 22 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_port[0] ; V10 ; 7 ; 33 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_port[1] ; A5 ; 4 ; 31 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_port[2] ; U10 ; 7 ; 30 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_port[3] ; P5 ; 6 ; 40 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_port[4] ; R1 ; 6 ; 40 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_port[5] ; U2 ; 6 ; 40 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ;; out_port[6] ; AA6 ; 7 ; 30 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_port[7] ; AB7 ; 7 ; 29 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;; out_rd_rdy ; Y16 ; 8 ; 13 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ;+-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------++------------------------------------------------------------+; I/O Bank Usage ;+----------+------------------+---------------+--------------+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;+----------+------------------+---------------+--------------+; 1 ; 16 / 40 ( 40 % ) ; 3.3V ; -- ;; 2 ; 12 / 44 ( 27 % ) ; 3.3V ; -- ;; 3 ; 18 / 50 ( 36 % ) ; 3.3V ; -- ;; 4 ; 15 / 35 ( 43 % ) ; 3.3V ; -- ;; 5 ; 14 / 44 ( 32 % ) ; 3.3V ; -- ;; 6 ; 23 / 40 ( 57 % ) ; 3.3V ; -- ;; 7 ; 20 / 34 ( 59 % ) ; 3.3V ; -- ;; 8 ; 17 / 43 ( 40 % ) ; 3.3V ; -- ;; 9 ; 5 / 6 ( 83 % ) ; 3.3V ; -- ;; 10 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ;+----------+------------------+---------------+--------------++--------------------------------------------------------------------------------------------------------------------------------------------------------+; All Package Pins ;+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A2 ; ; ; TEMPDIODEp ; ; ; ; -- ; ; -- ; -- ;; A3 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A4 ; 277 ; 4 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;; A5 ; 307 ; 4 ; out_port[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A6 ; 311 ; 4 ; in_data[23] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A7 ; 315 ; 4 ; in_data[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A8 ; 318 ; 4 ; in_data[15] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A10 ; 323 ; 9 ; in_data[33] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A11 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A13 ; 329 ; 3 ; in_data[55] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; A15 ; 343 ; 3 ; in_data[50] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; A16 ; 347 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A17 ; 351 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A18 ; 350 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A19 ; 375 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; A20 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; A21 ; 383 ; 3 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA3 ; 191 ; 7 ; ^nCEO ; ; ; ; -- ; ; -- ; -- ;; AA4 ; 181 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA5 ; 163 ; 7 ; in_ctrl[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA6 ; 159 ; 7 ; out_port[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA7 ; 155 ; 7 ; in_data[22] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA8 ; 151 ; 7 ; in_data[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA9 ; 144 ; 10 ; out_mac[31] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA10 ; 147 ; 10 ; out_mac[34] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA11 ; 141 ; 7 ; out_mac[19] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA12 ; 138 ; 8 ; out_mac[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA13 ; 137 ; 8 ; out_mac[45] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA14 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;; AA15 ; 127 ; 8 ; out_mac[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AA16 ; 123 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA17 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA18 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AA19 ; 85 ; 8 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;; AA20 ; 86 ; 8 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AA22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB2 ; 190 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; ; -- ; -- ;; AB3 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB5 ; 161 ; 7 ; out_mac[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB6 ; 157 ; 7 ; in_ctrl[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB7 ; 153 ; 7 ; out_port[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB8 ; 150 ; 7 ; out_mac[36] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB10 ; 145 ; 10 ; out_mac[26] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB11 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB13 ; 139 ; 8 ; out_mac[17] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; AB15 ; 125 ; 8 ; out_mac[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; AB16 ; 124 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB17 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB18 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; AB19 ; 87 ; 8 ; #TRST ; input ; ; ; -- ; ; -- ; -- ;; AB20 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; AB21 ; 84 ; 8 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B3 ; 276 ; 4 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;; B4 ; 279 ; 4 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;; B5 ; 305 ; 4 ; out_mac[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B6 ; 309 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B7 ; 313 ; 4 ; in_rd ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B8 ; 317 ; 4 ; in_data[12] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B9 ; 320 ; 9 ; in_data[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B10 ; 321 ; 9 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B11 ; 327 ; 4 ; in_data[32] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B12 ; 328 ; 4 ; in_data[43] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B13 ; 331 ; 3 ; in_data[61] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B14 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ;; B15 ; 341 ; 3 ; in_data[45] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; B16 ; 345 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B17 ; 349 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B18 ; 353 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B19 ; 377 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; B20 ; 381 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; B22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; C1 ; 275 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; C2 ; 273 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; C3 ; ; ; TEMPDIODEn ; ; ; ; -- ; ; -- ; -- ;; C4 ; 285 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C5 ; 306 ; 4 ; in_key[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C6 ; 308 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C7 ; 316 ; 4 ; in_data[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C8 ; 314 ; 4 ; in_data[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C9 ; 319 ; 9 ; in_data[13] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C10 ; 324 ; 9 ; in_data[41] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C11 ; 325 ; 4 ; in_data[42] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C12 ; 326 ; 4 ; in_data[37] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C13 ; 330 ; 3 ; out_mac[44] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C14 ; 354 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C15 ; 342 ; 3 ; in_data[48] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C16 ; 344 ; 3 ; in_data[51] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; C17 ; 352 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C18 ; 355 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C19 ; 369 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; C20 ; 384 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;; C21 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; C22 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D1 ; 271 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D2 ; 269 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D3 ; 287 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D4 ; 278 ; 4 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;; D5 ; 283 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D6 ; 293 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D7 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ;; D8 ; 297 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D9 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ;; D10 ; 322 ; 9 ; in_data[40] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D11 ; 337 ; 3 ; in_data[49] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D12 ; 333 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D13 ; 332 ; 3 ; in_data[8] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D14 ; 356 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D15 ; 361 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D16 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ;; D17 ; 373 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; D18 ; 379 ; 3 ; in_key[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D19 ; 382 ; 3 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ;; D20 ; 371 ; 3 ; in_key[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; D21 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; D22 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E1 ; 267 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E2 ; 265 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E3 ; 274 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E4 ; 272 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E5 ; 280 ; 4 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;; E6 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E7 ; 289 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E8 ; 298 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E9 ; 301 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E10 ; 312 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E11 ; 335 ; 3 ; out_mac[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E12 ; 339 ; 3 ; in_data[52] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E13 ; 338 ; 3 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E14 ; 357 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E15 ; 365 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E16 ; 374 ; 3 ; in_key[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; E17 ; 376 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E18 ; 380 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; E19 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E20 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E21 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; E22 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F1 ; 263 ; 5 ; in_key[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; F2 ; 261 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F3 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ;; F4 ; 270 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F5 ; 268 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F6 ; 288 ; 4 ; in_key[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; F7 ; 296 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F8 ; 294 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F9 ; 300 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F10 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ;; F11 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ;; F12 ; ; ; VCCA_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; F13 ; 346 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F14 ; 358 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F15 ; 367 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F16 ; 362 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F17 ; 378 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; F18 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ;; F19 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F20 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F21 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; F22 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G1 ; 255 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G2 ; 253 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G3 ; 262 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G4 ; 260 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G5 ; 266 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G6 ; 264 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G7 ; 286 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G8 ; 291 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G9 ; 302 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G10 ; ; 9 ; VCC_PLL5_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ;; G11 ; ; ; VCCD_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; G12 ; 336 ; 3 ; in_data[58] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; G13 ; 348 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G14 ; 359 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G15 ; 366 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G16 ; 370 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; G17 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G18 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G19 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G20 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G21 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; G22 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H1 ; 251 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H2 ; 249 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H3 ; 259 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H4 ; 257 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H5 ; 254 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H6 ; 252 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H7 ; 284 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; H9 ; 304 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H10 ; ; 4 ; VCCPD4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; H11 ; 334 ; 3 ; in_data[59] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; H12 ; 340 ; 3 ; in_data[47] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; H13 ; ; 3 ; VCCPD3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; H14 ; 360 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; H16 ; 368 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; H17 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H18 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H19 ; 18 ; 2 ; in_rdy ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; H20 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H21 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; H22 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J2 ; 247 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J3 ; 245 ; 5 ; in_data[34] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; J4 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ;; J5 ; 250 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J6 ; 248 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J7 ; 258 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J8 ; 256 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; J15 ; 364 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; J16 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J17 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J18 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J19 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J20 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J21 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; J22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K1 ; 239 ; 5 ; out_mac[25] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K2 ; 237 ; 5 ; in_data[60] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K3 ; 243 ; 5 ; in_data[62] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K4 ; 241 ; 5 ; in_data[25] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K5 ; 246 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K6 ; 244 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K7 ; 242 ; 5 ; out_mac[33] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K8 ; 240 ; 5 ; in_data[10] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; K14 ; ; 2 ; VCCPD2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; K15 ; 35 ; 2 ; in_data[63] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K16 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K17 ; 31 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K18 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; K19 ; 34 ; 2 ; in_data[31] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K20 ; 32 ; 2 ; in_data[30] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K21 ; 38 ; 2 ; in_data[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; K22 ; 36 ; 2 ; in_data[56] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L2 ; 233 ; 5 ; out_mac[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L3 ; 235 ; 5 ; in_data[35] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L4 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; L5 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ;; L6 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L7 ; 238 ; 5 ; in_data[57] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L8 ; 236 ; 5 ; in_data[14] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L9 ; ; 5 ; VCCPD5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; L15 ; 39 ; 2 ; in_data[11] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L16 ; 37 ; 2 ; in_data[54] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L17 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; L18 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ;; L19 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ;; L20 ; 40 ; 2 ; in_data[44] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L21 ; 42 ; 2 ; in_data[36] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; L22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; M2 ; 232 ; 5 ; in_data[38] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M3 ; 234 ; 5 ; in_data[39] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M4 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M6 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; M16 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M17 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M18 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M19 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; M20 ; 41 ; 2 ; in_data[46] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M21 ; 43 ; 2 ; reset ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; M22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; N1 ; 231 ; 6 ; in_data[16] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N2 ; 229 ; 6 ; in_data[27] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N3 ; 230 ; 6 ; in_data[19] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N4 ; 228 ; 6 ; in_data[26] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N5 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; N6 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ;; N7 ; 226 ; 6 ; out_mac[35] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N8 ; 224 ; 6 ; in_data[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N9 ; ; 6 ; VCCPD6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; N15 ; 51 ; 1 ; out_mac[43] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N16 ; 49 ; 1 ; out_mac[42] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N17 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; N18 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ;; N19 ; 47 ; 1 ; in_data[29] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N20 ; 45 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N21 ; 46 ; 1 ; out_mac[16] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; N22 ; 44 ; 1 ; in_data[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P2 ; 227 ; 6 ; out_mac[29] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P3 ; 225 ; 6 ; in_data[20] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P4 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ;; P5 ; 222 ; 6 ; out_port[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P6 ; 220 ; 6 ; in_data[28] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P7 ; 218 ; 6 ; out_mac[27] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P8 ; 216 ; 6 ; out_mac[24] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P10 ; ; 7 ; VCCPD7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;; P15 ; ; 1 ; VCCPD1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; P16 ; 59 ; 1 ; out_mac[41] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P17 ; 57 ; 1 ; out_mac[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P18 ; 55 ; 1 ; out_mac[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P19 ; 53 ; 1 ; out_mac[21] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P20 ; 50 ; 1 ; out_mac[46] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P21 ; 48 ; 1 ; out_mac[38] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; P22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R1 ; 223 ; 6 ; out_port[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R2 ; 221 ; 6 ; out_mac[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R3 ; 215 ; 6 ; in_data[21] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R4 ; 213 ; 6 ; in_data[17] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R5 ; 214 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R6 ; 212 ; 6 ; out_mac[40] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R7 ; 202 ; 6 ; in_ctrl[3] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R8 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R9 ; 168 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; R10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;; R11 ; ; 10 ; VCC_PLL6_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ;; R12 ; ; ; VCCA_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; R13 ; ; 8 ; VCCPD8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;; R14 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; R15 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; R16 ; 83 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R17 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R18 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R19 ; 61 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; R20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;; R21 ; 54 ; 1 ; out_mac[37] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; R22 ; 52 ; 1 ; out_mac[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T1 ; 219 ; 6 ; in_data[24] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T2 ; 217 ; 6 ; out_mac[30] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; T3 ; 207 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T4 ; 205 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T5 ; 210 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T6 ; 208 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T7 ; 186 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T8 ; 172 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T9 ; 170 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T10 ; 156 ; 7 ; in_ctrl[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; T11 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ;; T12 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ;; T13 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T14 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T15 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T16 ; 92 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; T17 ; 67 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T18 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T19 ; 66 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T20 ; 64 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T21 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; T22 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U1 ; 211 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U2 ; 209 ; 6 ; out_port[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U3 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ;; U4 ; 206 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U5 ; 204 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U6 ; 179 ; 7 ; out_rdy ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; U7 ; 180 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U8 ; 173 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U9 ; 171 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U10 ; 158 ; 7 ; out_port[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; U11 ; ; ; VCCD_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ;; U12 ; 130 ; 8 ; in_data[53] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; U13 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U14 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U15 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U16 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; U17 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U18 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U19 ; 70 ; 1 ; in_key[8] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; U20 ; 68 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U21 ; 62 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; U22 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V1 ; 203 ; 6 ; in_ctrl[5] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; V2 ; 201 ; 6 ; in_ctrl[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; V3 ; 198 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V4 ; 196 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V5 ; 188 ; 7 ; ^PORSEL ; ; ; ; -- ; ; -- ; -- ;; V6 ; 185 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V7 ; 175 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V8 ; 166 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V9 ; 149 ; 10 ; out_mac[22] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V10 ; 165 ; 7 ; out_port[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V11 ; 132 ; 8 ; out_mac[18] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V12 ; 134 ; 8 ; out_mac[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V13 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V14 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V15 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; V16 ; 93 ; 8 ; in_key[7] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; V17 ; 90 ; 8 ; ^VCCSEL ; ; ; ; -- ; ; -- ; -- ;; V18 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V19 ; 73 ; 1 ; in_key[9] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;; V20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ;; V21 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; V22 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W1 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W2 ; 197 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W3 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W4 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W5 ; 182 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W6 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;; W7 ; 177 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W8 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ;; W9 ; 148 ; 10 ; in_data[18] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W10 ; 142 ; 7 ; out_mac[32] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W11 ; 133 ; 8 ; out_mac[20] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W12 ; 135 ; 8 ; out_mac[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W13 ; 128 ; 8 ; out_mac[39] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W14 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W15 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W16 ; 101 ; 8 ; in_key[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; W17 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; W18 ; 88 ; 8 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;; W19 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W20 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W21 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; W22 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y1 ; 195 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y2 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y3 ; 184 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y4 ; 189 ; 7 ; PLL_ENA ; ; ; ; -- ; ; -- ; -- ;; Y5 ; 162 ; 7 ; out_mac[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y6 ; 160 ; 7 ; in_ctrl[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y7 ; 154 ; 7 ; in_wr ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y8 ; 152 ; 7 ; in_ctrl[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y9 ; 146 ; 10 ; in_data[6] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y10 ; 140 ; 7 ; out_mac[28] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y11 ; 143 ; 7 ; out_mac[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y12 ; 136 ; 8 ; out_mac[47] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y13 ; 131 ; 8 ; out_mac[23] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y14 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y15 ; 126 ; 8 ; out_mac[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y16 ; 121 ; 8 ; out_rd_rdy ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;; Y17 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y18 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y19 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ;; Y20 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;; Y21 ; 82 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;; Y22 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;+----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+Note: Pin directions (input, output or bidir) are based on device operating in user mode.+-------------------------------------------------------------------------------+; Output Pin Default Load For Reported TCO ;+----------------------------------+-------+------------------------------------+; I/O Standard ; Load ; Termination Resistance ;+----------------------------------+-------+------------------------------------+; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ;; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ;; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ;; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ;; LVDS ; 0 pF ; 100 Ohm (Differential) ;; HyperTransport ; 0 pF ; 100 Ohm (Differential) ;; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ;; 3.3-V LVTTL ; 0 pF ; Not Available ;; 3.3-V LVCMOS ; 0 pF ; Not Available ;; 2.5 V ; 0 pF ; Not Available ;; 1.8 V ; 0 pF ; Not Available ;; 1.5 V ; 0 pF ; Not Available ;; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ;; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ;; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ;; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ;; 1.2-V HSTL ; 0 pF ; Not Available ;; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ;; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ;; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ;; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ;; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ;; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ;; Differential 1.2-V HSTL ; 0 pF ; Not Available ;+----------------------------------+-------+------------------------------------+Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter Resource Utilization by Entity ;+-------------------------------------------------------+---------------------+----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+; Compilation Hierarchy Node ; Combinational ALUTs ; ALMs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Combinational with no register ; Register-Only ; Combinational with a register ; Full Hierarchy Name ; Library Name ;; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ALUT/register pair ; ALUT/register pair ; ALUT/register pair ; ; ;+-------------------------------------------------------+---------------------+----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+; |LB ; 534 (1) ; 524 (1) ; 870 (0) ; 0 (0) ; 154560 ; 3 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; 145 ; 0 ; 143 (1) ; 489 (0) ; 381 (0) ; |LB ; work ;; |manager:inst| ; 533 (27) ; 523 (49) ; 870 (90) ; 0 (0) ; 154560 ; 3 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 142 (6) ; 489 (70) ; 381 (20) ; |LB|manager:inst ; work ;; |table:table_Inst| ; 506 (57) ; 478 (23) ; 780 (24) ; 0 (0) ; 154560 ; 3 ; 39 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 136 (20) ; 419 (0) ; 361 (35) ; |LB|manager:inst|table:table_Inst ; work ;; |mac_ram_table:ram_Inst| ; 408 (143) ; 367 (80) ; 594 (96) ; 0 (0) ; 138176 ; 3 ; 35 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 105 (52) ; 287 (30) ; 307 (87) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst ; work ;; |Aging_Timer:Aging_Timer_Inst| ; 42 (42) ; 23 (23) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 0 (0) ; 33 (33) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Aging_Timer:Aging_Timer_Inst ; work ;; |ram_256x48:Aging_Valid_256x48_Inst| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst ; work ;; |altsyncram:ram_rtl_3| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3 ; work ;; |altsyncram_pvi1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 2048 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated ; work ;; |ram_256x48:ram_256x48_Inst| ; 6 (6) ; 86 (86) ; 133 (133) ; 0 (0) ; 57344 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 112 (112) ; 21 (21) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst ; work ;; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 57344 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|altsyncram:ram_rtl_0 ; work ;; |altsyncram_b3j1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 57344 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|altsyncram:ram_rtl_0|altsyncram_b3j1:auto_generated ; work ;; |ram_256x48:ram_256x48_search_Inst| ; 6 (6) ; 48 (48) ; 64 (64) ; 0 (0) ; 57344 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 64 (64) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst ; work ;; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 57344 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2 ; work ;; |altsyncram_b3j1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 57344 ; 0 ; 14 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated ; work ;; |small_fifo:WRITE_command_Inst| ; 27 (27) ; 22 (22) ; 31 (31) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 12 (12) ; 19 (19) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst ; work ;; |altsyncram:queue_rtl_5| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|altsyncram:queue_rtl_5 ; work ;; |altsyncram_rpi1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|altsyncram:queue_rtl_5|altsyncram_rpi1:auto_generated ; work ;; |small_fifo:time_command_Inst| ; 3 (3) ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 2 (2) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:time_command_Inst ; work ;; |valid_address:valid_address_Inst| ; 182 (99) ; 154 (42) ; 235 (74) ; 0 (0) ; 21120 ; 2 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 25 (9) ; 69 (5) ; 177 (89) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst ; work ;; |ram_256x48:valid_mac_256x48_Inst| ; 15 (15) ; 26 (26) ; 31 (31) ; 0 (0) ; 10240 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 25 (25) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst ; work ;; |altsyncram:ram_rtl_4| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|altsyncram:ram_rtl_4 ; work ;; |altsyncram_n2j1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|altsyncram:ram_rtl_4|altsyncram_n2j1:auto_generated ; work ;; |ram_256x48:valid_mac_Map_256x48_Inst| ; 6 (6) ; 27 (27) ; 40 (40) ; 0 (0) ; 10240 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 24 (24) ; 16 (16) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_Map_256x48_Inst ; work ;; |altsyncram:ram_rtl_7| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_Map_256x48_Inst|altsyncram:ram_rtl_7 ; work ;; |altsyncram_n2j1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 10240 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_Map_256x48_Inst|altsyncram:ram_rtl_7|altsyncram_n2j1:auto_generated ; work ;; |small_fifo:read_command_Inst| ; 9 (9) ; 5 (5) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 6 (6) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst ; work ;; |small_fifo:remove_command_Inst| ; 28 (28) ; 34 (34) ; 42 (42) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 (8) ; 12 (12) ; 30 (30) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst ; work ;; |altsyncram:queue_rtl_8| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|altsyncram:queue_rtl_8 ; work ;; |altsyncram_rpi1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|altsyncram:queue_rtl_8|altsyncram_rpi1:auto_generated ; work ;; |small_fifo:write_command_Inst| ; 26 (26) ; 30 (30) ; 42 (42) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 12 (12) ; 31 (31) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst ; work ;; |altsyncram:queue_rtl_6| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|altsyncram:queue_rtl_6 ; work ;; |altsyncram_rpi1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 320 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|altsyncram:queue_rtl_6|altsyncram_rpi1:auto_generated ; work ;; |small_fifo:small_fifo_Inst| ; 42 (42) ; 92 (92) ; 162 (162) ; 0 (0) ; 16384 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 132 (132) ; 30 (30) ; |LB|manager:inst|table:table_Inst|small_fifo:small_fifo_Inst ; work ;; |altsyncram:queue_rtl_1| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1 ; work ;; |altsyncram_3ui1:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |LB|manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_3ui1:auto_generated ; work ;+-------------------------------------------------------+---------------------+----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.+-------------------------------------------------------------------------------------------------------------------------------+; Delay Chain Summary ;+-------------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; DQS bus ; NDQS bus ; DQS output ;+-------------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------+; in_rdy ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_rdy ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[9] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[8] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[7] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[6] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[5] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[4] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[3] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[2] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[1] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_key[0] ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; out_rd_rdy ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[47] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[46] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[45] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[44] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[43] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[42] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[41] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[40] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[39] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[38] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[37] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[36] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[35] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[34] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[33] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[32] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[31] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[30] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[29] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[28] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[27] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[26] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[25] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[24] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[23] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[22] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[21] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[20] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[19] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[18] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[17] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[16] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[15] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[14] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[13] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[12] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[11] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[10] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[9] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[8] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[7] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[6] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[5] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[4] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[3] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[2] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[1] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_mac[0] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[7] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[6] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[5] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[4] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[3] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[2] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[1] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; out_port[0] ; Output ; -- ; -- ; -- ; -- ; 0 ; -- ; -- ; -- ;; clk ; Input ; 0 ; 0 ; -- ; -- ; -- ; -- ; -- ; -- ;; reset ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_wr ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[3] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[5] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[4] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[7] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[2] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[6] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[1] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_ctrl[0] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[63] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[62] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[61] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[60] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[59] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[58] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[57] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[56] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[55] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[54] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[53] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[52] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[51] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[50] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[49] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[48] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[47] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[46] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[45] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[44] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[43] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[42] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[41] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[40] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[39] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[38] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[37] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[36] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[35] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[34] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[33] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[32] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[31] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[30] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[29] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[28] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[27] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[26] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[25] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[24] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[23] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[22] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[21] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[20] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[19] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[18] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[17] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[16] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[7] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[6] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[5] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[4] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[3] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[2] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[1] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[0] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_rd ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[13] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[15] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[14] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[12] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[11] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[10] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[9] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;; in_data[8] ; Input ; 7 ; 7 ; -- ; -- ; -- ; -- ; -- ; -- ;+-------------+----------+---------------+---------------+-----------------------+-----+------+---------+----------+------------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Pad To Core Delay Chain Fanout ;+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+; Source Pin / Fanout ; Pad To Core Index ; Setting ;+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------+; out_rdy ; ; ;; in_key[9] ; ; ;; in_key[8] ; ; ;; in_key[7] ; ; ;; in_key[6] ; ; ;; in_key[5] ; ; ;; in_key[4] ; ; ;; in_key[3] ; ; ;; in_key[2] ; ; ;; in_key[1] ; ; ;; in_key[0] ; ; ;; clk ; ; ;; reset ; ; ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[6] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|wr_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|wr_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|wr_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|wr_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|wr_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[7] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[9] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[8] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[7] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[6] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[8] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[7] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[6] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|out_rd_rdy_i ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|out_rd_rdy ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[7] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[6] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[9] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[8] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[7] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[6] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[5] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[4] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[3] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[2] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[1] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|out_rdy ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|out_rdy_ii ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 ; 1 ; 7 ;; - manager:inst|mac_wr ; 1 ; 7 ;; - manager:inst|mac[47] ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~112 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~113 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~114 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~115 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~116 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~117 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~118 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|rd_ptr~119 ; 1 ; 7 ;; - manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[2]~254 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|in_mac_no_prt_i[55]~1863 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[9]~223 ; 1 ; 7 ;; - manager:inst|mac[46] ; 1 ; 7 ;; - manager:inst|mac[45] ; 1 ; 7 ;; - manager:inst|mac[44] ; 1 ; 7 ;; - manager:inst|mac[43] ; 1 ; 7 ;; - manager:inst|mac[42] ; 1 ; 7 ;; - manager:inst|mac[41] ; 1 ; 7 ;; - manager:inst|mac[40] ; 1 ; 7 ;; - manager:inst|mac[39] ; 1 ; 7 ;; - manager:inst|mac[38] ; 1 ; 7 ;; - manager:inst|mac[37] ; 1 ; 7 ;; - manager:inst|mac[36] ; 1 ; 7 ;; - manager:inst|mac[35] ; 1 ; 7 ;; - manager:inst|mac[34] ; 1 ; 7 ;; - manager:inst|mac[33] ; 1 ; 7 ;; - manager:inst|mac[32] ; 1 ; 7 ;; - manager:inst|mac[31] ; 1 ; 7 ;; - manager:inst|mac[30] ; 1 ; 7 ;; - manager:inst|mac[29] ; 1 ; 7 ;; - manager:inst|mac[28] ; 1 ; 7 ;; - manager:inst|mac[27] ; 1 ; 7 ;; - manager:inst|mac[26] ; 1 ; 7 ;; - manager:inst|mac[25] ; 1 ; 7 ;; - manager:inst|mac[24] ; 1 ; 7 ;; - manager:inst|mac[23] ; 1 ; 7 ;; - manager:inst|mac[22] ; 1 ; 7 ;; - manager:inst|mac[21] ; 1 ; 7 ;; - manager:inst|mac[20] ; 1 ; 7 ;; - manager:inst|mac[19] ; 1 ; 7 ;; - manager:inst|mac[18] ; 1 ; 7 ;; - manager:inst|mac[17] ; 1 ; 7 ;; - manager:inst|mac[16] ; 1 ; 7 ;; - manager:inst|mac[15] ; 1 ; 7 ;; - manager:inst|mac[14] ; 1 ; 7 ;; - manager:inst|mac[13] ; 1 ; 7 ;; - manager:inst|mac[12] ; 1 ; 7 ;; - manager:inst|mac[11] ; 1 ; 7 ;; - manager:inst|mac[10] ; 1 ; 7 ;; - manager:inst|mac[9] ; 1 ; 7 ;; - manager:inst|mac[8] ; 1 ; 7 ;; - manager:inst|mac[7] ; 1 ; 7 ;; - manager:inst|mac[6] ; 1 ; 7 ;; - manager:inst|mac[5] ; 1 ; 7 ;; - manager:inst|mac[4] ; 1 ; 7 ;; - manager:inst|mac[3] ; 1 ; 7 ;; - manager:inst|mac[2] ; 1 ; 7 ;; - manager:inst|mac[1] ; 1 ; 7 ;; - manager:inst|mac[0] ; 1 ; 7 ;; - manager:inst|mac_exit_port[7] ; 1 ; 7 ;; - manager:inst|mac_exit_port[6] ; 1 ; 7 ;; - manager:inst|mac_exit_port[5] ; 1 ; 7 ;; - manager:inst|mac_exit_port[4] ; 1 ; 7 ;; - manager:inst|mac_exit_port[3] ; 1 ; 7 ;; - manager:inst|mac_exit_port[2] ; 1 ; 7 ;; - manager:inst|mac_exit_port[1] ; 1 ; 7 ;; - manager:inst|mac_exit_port[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~225 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~226 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~227 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~228 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~229 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~230 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~231 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~232 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~233 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 ; 1 ; 7 ;; - manager:inst|mac_cnt[31]~344 ; 1 ; 7 ;; - manager:inst|mac_weight[5] ; 1 ; 7 ;; - manager:inst|mac_weight[7] ; 1 ; 7 ;; - manager:inst|mac_weight[6] ; 1 ; 7 ;; - manager:inst|mac_weight[4] ; 1 ; 7 ;; - manager:inst|mac_weight[3] ; 1 ; 7 ;; - manager:inst|mac_weight[2] ; 1 ; 7 ;; - manager:inst|mac_weight[1] ; 1 ; 7 ;; - manager:inst|mac_weight[0] ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr~70 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr~71 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr~72 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr~73 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|rd_ptr~74 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[4]~1074 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[1]~1107 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[4]~1115 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|\process7:cnt1[2]~7 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr~72 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr~73 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr~74 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr~75 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|rd_ptr~76 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[1]~435 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr~70 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr~71 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr~72 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr~73 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|rd_ptr~74 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:time_command_Inst|depth[1]~264 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:time_command_Inst|depth[0]~265 ; 1 ; 7 ;; in_wr ; ; ;; - manager:inst|Add0~120 ; 0 ; 7 ;; - manager:inst|done_macs_up~27 ; 0 ; 7 ;; - manager:inst|state.word_6 ; 0 ; 7 ;; - manager:inst|Selector3~104 ; 0 ; 7 ;; - manager:inst|mac_cnt[31]~344 ; 0 ; 7 ;; - manager:inst|Selector0~22 ; 0 ; 7 ;; - manager:inst|state.word_5 ; 0 ; 7 ;; - manager:inst|Selector1~173 ; 0 ; 7 ;; - manager:inst|process2~71 ; 0 ; 7 ;; - manager:inst|state.word_4 ; 0 ; 7 ;; - manager:inst|state.word_3 ; 0 ; 7 ;; - manager:inst|state.word_2 ; 0 ; 7 ;; - manager:inst|Selector4~47 ; 0 ; 7 ;; in_ctrl[3] ; ; ;; - manager:inst|Equal1~46 ; 1 ; 7 ;; - manager:inst|process2~0 ; 1 ; 7 ;; in_ctrl[5] ; ; ;; - manager:inst|Equal1~46 ; 0 ; 7 ;; - manager:inst|process2~0 ; 0 ; 7 ;; in_ctrl[4] ; ; ;; - manager:inst|Equal1~46 ; 0 ; 7 ;; - manager:inst|process2~71 ; 0 ; 7 ;; in_ctrl[7] ; ; ;; - manager:inst|Equal1~45 ; 0 ; 7 ;; - manager:inst|process2~71 ; 0 ; 7 ;; in_ctrl[2] ; ; ;; - manager:inst|Equal1~45 ; 0 ; 7 ;; - manager:inst|process2~0 ; 0 ; 7 ;; in_ctrl[6] ; ; ;; - manager:inst|Equal1~45 ; 0 ; 7 ;; - manager:inst|process2~0 ; 0 ; 7 ;; in_ctrl[1] ; ; ;; - manager:inst|Equal1~45 ; 0 ; 7 ;; - manager:inst|process2~0 ; 0 ; 7 ;; in_ctrl[0] ; ; ;; - manager:inst|Equal1~45 ; 0 ; 7 ;; - manager:inst|process2~71 ; 0 ; 7 ;; in_data[63] ; ; ;; - manager:inst|mac[47]~feeder ; 0 ; 7 ;; in_data[62] ; ; ;; - manager:inst|mac[46]~feeder ; 0 ; 7 ;; in_data[61] ; ; ;; - manager:inst|mac[45]~feeder ; 0 ; 7 ;; in_data[60] ; ; ;; - manager:inst|mac[44]~feeder ; 1 ; 7 ;; in_data[59] ; ; ;; - manager:inst|mac[43]~feeder ; 0 ; 7 ;; in_data[58] ; ; ;; - manager:inst|mac[42]~feeder ; 1 ; 7 ;; in_data[57] ; ; ;; - manager:inst|mac[41]~feeder ; 1 ; 7 ;; in_data[56] ; ; ;; - manager:inst|mac[40]~feeder ; 0 ; 7 ;; in_data[55] ; ; ;; - manager:inst|mac[39]~feeder ; 1 ; 7 ;; in_data[54] ; ; ;; - manager:inst|mac[38]~feeder ; 1 ; 7 ;; in_data[53] ; ; ;; - manager:inst|mac[37]~feeder ; 0 ; 7 ;; in_data[52] ; ; ;; - manager:inst|mac[36]~feeder ; 1 ; 7 ;; in_data[51] ; ; ;; - manager:inst|mac[35]~feeder ; 0 ; 7 ;; in_data[50] ; ; ;; - manager:inst|mac[34]~feeder ; 0 ; 7 ;; in_data[49] ; ; ;; - manager:inst|mac[33]~feeder ; 1 ; 7 ;; in_data[48] ; ; ;; - manager:inst|mac[32]~feeder ; 0 ; 7 ;; in_data[47] ; ; ;; - manager:inst|mac[31]~feeder ; 0 ; 7 ;; in_data[46] ; ; ;; - manager:inst|mac[30]~feeder ; 1 ; 7 ;; in_data[45] ; ; ;; - manager:inst|mac[29]~feeder ; 1 ; 7 ;; in_data[44] ; ; ;; - manager:inst|mac[28] ; 1 ; 7 ;; in_data[43] ; ; ;; - manager:inst|mac[27]~feeder ; 0 ; 7 ;; in_data[42] ; ; ;; - manager:inst|mac[26]~feeder ; 0 ; 7 ;; in_data[41] ; ; ;; - manager:inst|mac[25]~feeder ; 0 ; 7 ;; in_data[40] ; ; ;; - manager:inst|mac[24]~feeder ; 1 ; 7 ;; in_data[39] ; ; ;; - manager:inst|mac[23] ; 0 ; 7 ;; in_data[38] ; ; ;; - manager:inst|mac[22]~feeder ; 1 ; 7 ;; in_data[37] ; ; ;; - manager:inst|mac[21] ; 1 ; 7 ;; in_data[36] ; ; ;; - manager:inst|mac[20] ; 0 ; 7 ;; in_data[35] ; ; ;; - manager:inst|mac[19]~feeder ; 1 ; 7 ;; in_data[34] ; ; ;; - manager:inst|mac[18] ; 0 ; 7 ;; in_data[33] ; ; ;; - manager:inst|mac[17]~feeder ; 0 ; 7 ;; in_data[32] ; ; ;; - manager:inst|mac[16]~feeder ; 1 ; 7 ;; in_data[31] ; ; ;; - manager:inst|mac_cnt[7] ; 1 ; 7 ;; - manager:inst|mac[15] ; 1 ; 7 ;; in_data[30] ; ; ;; - manager:inst|mac_cnt[6] ; 1 ; 7 ;; - manager:inst|mac[14] ; 1 ; 7 ;; in_data[29] ; ; ;; - manager:inst|mac_cnt[5] ; 1 ; 7 ;; - manager:inst|mac[13] ; 1 ; 7 ;; in_data[28] ; ; ;; - manager:inst|mac_cnt[4] ; 1 ; 7 ;; - manager:inst|mac[12] ; 1 ; 7 ;; in_data[27] ; ; ;; - manager:inst|mac_cnt[3] ; 0 ; 7 ;; - manager:inst|mac[11]~feeder ; 0 ; 7 ;; in_data[26] ; ; ;; - manager:inst|mac_cnt[2] ; 0 ; 7 ;; - manager:inst|mac[10]~feeder ; 0 ; 7 ;; in_data[25] ; ; ;; - manager:inst|mac_cnt[1] ; 1 ; 7 ;; - manager:inst|mac[9] ; 1 ; 7 ;; in_data[24] ; ; ;; - manager:inst|mac[8] ; 1 ; 7 ;; - manager:inst|mac_cnt[0]~345 ; 1 ; 7 ;; in_data[23] ; ; ;; - manager:inst|mac[7]~feeder ; 0 ; 7 ;; in_data[22] ; ; ;; - manager:inst|mac[6] ; 0 ; 7 ;; in_data[21] ; ; ;; - manager:inst|mac[5] ; 1 ; 7 ;; in_data[20] ; ; ;; - manager:inst|mac[4] ; 1 ; 7 ;; in_data[19] ; ; ;; - manager:inst|mac[3]~feeder ; 0 ; 7 ;; in_data[18] ; ; ;; - manager:inst|mac[2]~feeder ; 1 ; 7 ;; in_data[17] ; ; ;; - manager:inst|mac[1]~feeder ; 1 ; 7 ;; in_data[16] ; ; ;; - manager:inst|mac[0] ; 0 ; 7 ;; in_data[7] ; ; ;; - manager:inst|mac_exit_port[7]~feeder ; 1 ; 7 ;; in_data[6] ; ; ;; - manager:inst|mac_exit_port[6] ; 0 ; 7 ;; in_data[5] ; ; ;; - manager:inst|mac_exit_port[5] ; 0 ; 7 ;; in_data[4] ; ; ;; - manager:inst|mac_exit_port[4]~feeder ; 1 ; 7 ;; in_data[3] ; ; ;; - manager:inst|mac_exit_port[3] ; 0 ; 7 ;; in_data[2] ; ; ;; - manager:inst|mac_exit_port[2] ; 0 ; 7 ;; in_data[1] ; ; ;; - manager:inst|mac_exit_port[1] ; 1 ; 7 ;; in_data[0] ; ; ;; - manager:inst|mac_exit_port[0]~feeder ; 1 ; 7 ;; in_rd ; ; ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|Add2~132 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|Add2~136 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|Add2~140 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|Add2~144 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|Add2~148 ; 1 ; 7 ;; - manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[4]~1115 ; 1 ; 7 ;; in_data[13] ; ; ;; - manager:inst|mac_weight[5]~feeder ; 0 ; 7 ;; in_data[15] ; ; ;; - manager:inst|mac_weight[7] ; 1 ; 7 ;; in_data[14] ; ; ;; - manager:inst|mac_weight[6]~feeder ; 1 ; 7 ;; in_data[12] ; ; ;; - manager:inst|mac_weight[4]~feeder ; 0 ; 7 ;; in_data[11] ; ; ;; - manager:inst|mac_weight[3]~feeder ; 1 ; 7 ;; in_data[10] ; ; ;; - manager:inst|mac_weight[2]~feeder ; 0 ; 7 ;; in_data[9] ; ; ;; - manager:inst|mac_weight[1]~feeder ; 0 ; 7 ;; in_data[8] ; ; ;; - manager:inst|mac_weight[0]~feeder ; 0 ; 7 ;+-------------------------------------------------------------------------------------------------------------------------------------------+-------------------+---------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Control Signals ;+------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------+; clk ; PIN_N20 ; 912 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ;; in_wr ; PIN_Y7 ; 13 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|Selector0~22 ; LCCOMB_X30_Y11_N22 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ;; manager:inst|mac_cnt[31]~344 ; LCCOMB_X29_Y11_N22 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|mac_wr ; LCFF_X30_Y11_N19 ; 15 ; Write enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|cnt[5]~51 ; LCCOMB_X23_Y18_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|fifo_rd~43 ; LCCOMB_X23_Y18_N22 ; 66 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Aging_Timer:Aging_Timer_Inst|Equal0~179 ; LCCOMB_X13_Y18_N24 ; 33 ; Sync. clear ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector29~25 ; LCCOMB_X13_Y12_N0 ; 2 ; Write enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector29~26 ; LCCOMB_X13_Y11_N8 ; 1 ; Write enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|\process7:cnt1[2]~7 ; LCCOMB_X14_Y10_N28 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|in_mac_no_prt_i[55]~1863 ; LCCOMB_X22_Y9_N2 ; 56 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 ; LCCOMB_X21_Y9_N18 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~455 ; LCCOMB_X19_Y13_N12 ; 56 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|ram~386 ; LCCOMB_X18_Y12_N12 ; 56 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|depth[1]~435 ; LCCOMB_X14_Y10_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|queue~92 ; LCCOMB_X14_Y13_N8 ; 10 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|state_next.add_1~30 ; LCCOMB_X14_Y10_N22 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|cnt[9]~223 ; LCCOMB_X22_Y15_N28 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|current_up ; LCFF_X22_Y15_N9 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|map_waddr[0]~33 ; LCCOMB_X18_Y14_N18 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|map_wr_en ; LCFF_X18_Y15_N21 ; 7 ; Write enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|process5~21 ; LCCOMB_X22_Y15_N8 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_Map_256x48_Inst|ram~178 ; LCCOMB_X17_Y15_N24 ; 10 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:read_command_Inst|depth[4]~1115 ; LCCOMB_X26_Y17_N18 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|depth[4]~1074 ; LCCOMB_X13_Y12_N6 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|queue~103 ; LCCOMB_X14_Y11_N6 ; 10 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|depth[1]~1107 ; LCCOMB_X14_Y10_N20 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|queue~105 ; LCCOMB_X18_Y10_N18 ; 10 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.add_1 ; LCFF_X17_Y10_N29 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.remove_1 ; LCFF_X22_Y15_N7 ; 19 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|vd_add_wr~3 ; LCCOMB_X17_Y10_N30 ; 2 ; Write enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|depth[2]~254 ; LCCOMB_X23_Y18_N20 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|queue~401 ; LCCOMB_X18_Y18_N8 ; 64 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|state.add_entry ; LCFF_X21_Y12_N25 ; 27 ; Clock enable ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|state.idle ; LCFF_X22_Y12_N25 ; 20 ; Sync. clear ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|state.latch_mac_lookup ; LCFF_X21_Y12_N7 ; 24 ; Sync. load ; no ; -- ; -- ; -- ;; manager:inst|table:table_Inst|state_next~63 ; LCCOMB_X18_Y12_N14 ; 34 ; Write enable ; no ; -- ; -- ; -- ;; reset ; PIN_M21 ; 214 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;; reset ; PIN_M21 ; 73 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ;+------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+---------------------------+--------+----------------------+------------------+---------------------------++--------------------------------------------------------------------------------------------------+; Global & Other Fast Signals ;+-------+----------+---------+----------------------+------------------+---------------------------+; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;+-------+----------+---------+----------------------+------------------+---------------------------+; clk ; PIN_N20 ; 912 ; Global Clock ; GCLK3 ; -- ;; reset ; PIN_M21 ; 73 ; Global Clock ; GCLK1 ; -- ;+-------+----------+---------+----------------------+------------------+---------------------------++------------------------------------------------------------------------------------------------------------------------------------------+; Non-Global High Fan-Out Signals ;+--------------------------------------------------------------------------------------------------------------------------------+---------+; Name ; Fan-Out ;+--------------------------------------------------------------------------------------------------------------------------------+---------+; reset ; 213 ;; manager:inst|table:table_Inst|fifo_rd~43 ; 66 ;; manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|queue~401 ; 64 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|ram~386 ; 56 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|in_mac_no_prt_i[55]~1863 ; 56 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~455 ; 56 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.remove_4 ; 43 ;; manager:inst|table:table_Inst|state_next~63 ; 34 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Aging_Timer:Aging_Timer_Inst|Equal0~179 ; 33 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|state.scan_2 ; 32 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.add_2 ; 32 ;; manager:inst|table:table_Inst|Selector6~8 ; 30 ;; manager:inst|table:table_Inst|Selector7~8 ; 30 ;; manager:inst|table:table_Inst|Selector8~8 ; 30 ;; manager:inst|table:table_Inst|Selector9~8 ; 30 ;; manager:inst|table:table_Inst|Selector10~8 ; 30 ;; manager:inst|table:table_Inst|Selector11~8 ; 30 ;; manager:inst|table:table_Inst|Selector12~8 ; 30 ;; manager:inst|table:table_Inst|Selector13~8 ; 30 ;; manager:inst|table:table_Inst|Selector14~8 ; 30 ;; manager:inst|table:table_Inst|Selector15~8 ; 30 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 ; 28 ;; manager:inst|table:table_Inst|state.add_entry ; 27 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal2~74 ; 26 ;; manager:inst|table:table_Inst|state.latch_mac_lookup ; 24 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|state.add_2 ; 22 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.remove_2 ; 21 ;; manager:inst|table:table_Inst|state.idle ; 20 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.remove_1 ; 19 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|state.add_1 ; 18 ;; manager:inst|table:table_Inst|state.update_entry ; 17 ;; manager:inst|mac_wr ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~307 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~306 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~305 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~304 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~303 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~302 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~301 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~300 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~299 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|ram~298 ; 15 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~233 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~232 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~231 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~230 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~229 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~228 ; 14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~227 ; 14 ;+--------------------------------------------------------------------------------------------------------------------------------+---------++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Fitter RAM Summary ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M512s ; M4Ks ; M-RAMs ; MIF ; Location ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1024 ; 2 ; 1024 ; 2 ; yes ; no ; yes ; no ; 2048 ; 1024 ; 2 ; 1024 ; 2 ; 2048 ; 0 ; 1 ; 0 ; None ; M4K_X8_Y10 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|altsyncram:ram_rtl_0|altsyncram_b3j1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1024 ; 56 ; 1024 ; 56 ; yes ; no ; yes ; no ; 57344 ; 1024 ; 56 ; 1024 ; 56 ; 57344 ; 0 ; 14 ; 0 ; None ; M4K_X20_Y9, M4K_X32_Y5, M4K_X20_Y7, M4K_X20_Y13, M4K_X20_Y11, M4K_X32_Y7, M4K_X20_Y12, M4K_X20_Y5, M4K_X20_Y8, M4K_X32_Y8, M4K_X20_Y6, M4K_X32_Y13, M4K_X32_Y12, M4K_X32_Y9 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1024 ; 56 ; 1024 ; 56 ; yes ; no ; yes ; no ; 57344 ; 1024 ; 56 ; 1024 ; 56 ; 57344 ; 0 ; 14 ; 0 ; None ; M4K_X8_Y8, M4K_X20_Y4, M4K_X8_Y9, M4K_X32_Y6, M4K_X32_Y3, M4K_X8_Y6, M4K_X20_Y10, M4K_X32_Y10, M4K_X32_Y11, M4K_X32_Y4, M4K_X8_Y11, M4K_X8_Y12, M4K_X20_Y3, M4K_X8_Y7 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|altsyncram:queue_rtl_5|altsyncram_rpi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 10 ; 32 ; 10 ; yes ; no ; yes ; no ; 320 ; 32 ; 10 ; 32 ; 10 ; 320 ; 1 ; 0 ; 0 ; None ; M512_X16_Y13 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_256x48_Inst|altsyncram:ram_rtl_4|altsyncram_n2j1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1024 ; 10 ; 1024 ; 10 ; yes ; no ; yes ; no ; 10240 ; 1024 ; 10 ; 1024 ; 10 ; 10240 ; 0 ; 3 ; 0 ; None ; M4K_X32_Y15, M4K_X20_Y14, M4K_X32_Y14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|ram_256x48:valid_mac_Map_256x48_Inst|altsyncram:ram_rtl_7|altsyncram_n2j1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 1024 ; 10 ; 1024 ; 10 ; yes ; no ; yes ; no ; 10240 ; 1024 ; 10 ; 1024 ; 10 ; 10240 ; 0 ; 3 ; 0 ; None ; M4K_X8_Y15, M4K_X20_Y15, M4K_X8_Y14 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|altsyncram:queue_rtl_8|altsyncram_rpi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 10 ; 32 ; 10 ; yes ; no ; yes ; no ; 320 ; 32 ; 10 ; 32 ; 10 ; 320 ; 1 ; 0 ; 0 ; None ; M512_X16_Y11 ;; manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:write_command_Inst|altsyncram:queue_rtl_6|altsyncram_rpi1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 32 ; 10 ; 32 ; 10 ; yes ; no ; yes ; no ; 320 ; 32 ; 10 ; 32 ; 10 ; 320 ; 1 ; 0 ; 0 ; None ; M512_X16_Y10 ;; manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_3ui1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 256 ; 64 ; 256 ; 64 ; yes ; no ; yes ; no ; 16384 ; 256 ; 64 ; 256 ; 64 ; 16384 ; 0 ; 4 ; 0 ; None ; M4K_X20_Y18, M4K_X20_Y16, M4K_X20_Y17, M4K_X32_Y17 ;+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.+--------------------------------------------------------------------+; Interconnect Usage Summary ;+-------------------------------------------+------------------------+; Interconnect Resource Type ; Usage ;+-------------------------------------------+------------------------+; Block interconnects ; 2,442 / 51,960 ( 5 % ) ;; C16 interconnects ; 47 / 1,680 ( 3 % ) ;; C4 interconnects ; 1,516 / 38,400 ( 4 % ) ;; DPA clocks ; 0 / 4 ( 0 % ) ;; DQS bus muxes ; 0 / 18 ( 0 % ) ;; DQS-18 I/O buses ; 0 / 4 ( 0 % ) ;; DQS-4 I/O buses ; 0 / 18 ( 0 % ) ;; DQS-9 I/O buses ; 0 / 8 ( 0 % ) ;; Differential I/O clocks ; 0 / 32 ( 0 % ) ;; Direct links ; 184 / 51,960 ( < 1 % ) ;; Global clocks ; 2 / 16 ( 13 % ) ;; Local interconnects ; 356 / 12,480 ( 3 % ) ;; NDQS bus muxes ; 0 / 18 ( 0 % ) ;; NDQS-18 I/O buses ; 0 / 4 ( 0 % ) ;; NDQS-4 I/O buses ; 0 / 18 ( 0 % ) ;; NDQS-9 I/O buses ; 0 / 8 ( 0 % ) ;; PLL transmitter or receiver load enables ; 0 / 8 ( 0 % ) ;; PLL transmitter or receiver synch. clocks ; 0 / 8 ( 0 % ) ;; R24 interconnects ; 62 / 1,664 ( 4 % ) ;; R24/C16 interconnect drivers ; 38 / 4,160 ( < 1 % ) ;; R4 interconnects ; 2,652 / 59,488 ( 4 % ) ;; Regional clocks ; 0 / 32 ( 0 % ) ;+-------------------------------------------+------------------------++---------------------------------------------------------------------------+; LAB Logic Elements ;+--------------------------------------------+------------------------------+; Number of Logic Elements (Average = 6.81) ; Number of LABs (Total = 77) ;+--------------------------------------------+------------------------------+; 1 ; 6 ;; 2 ; 2 ;; 3 ; 3 ;; 4 ; 1 ;; 5 ; 4 ;; 6 ; 2 ;; 7 ; 3 ;; 8 ; 56 ;+--------------------------------------------+------------------------------++-------------------------------------------------------------------+; LAB-wide Signals ;+------------------------------------+------------------------------+; LAB-wide Signals (Average = 2.10) ; Number of LABs (Total = 77) ;+------------------------------------+------------------------------+; 1 Async. clear ; 17 ;; 1 Clock ; 75 ;; 1 Clock enable ; 31 ;; 1 Sync. clear ; 10 ;; 1 Sync. load ; 25 ;; 2 Clock enables ; 4 ;+------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Signals Sourced ;+----------------------------------------------+------------------------------+; Number of Signals Sourced (Average = 20.62) ; Number of LABs (Total = 77) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 3 ;; 2 ; 2 ;; 3 ; 0 ;; 4 ; 2 ;; 5 ; 0 ;; 6 ; 1 ;; 7 ; 0 ;; 8 ; 2 ;; 9 ; 2 ;; 10 ; 2 ;; 11 ; 0 ;; 12 ; 2 ;; 13 ; 0 ;; 14 ; 5 ;; 15 ; 2 ;; 16 ; 5 ;; 17 ; 2 ;; 18 ; 1 ;; 19 ; 3 ;; 20 ; 0 ;; 21 ; 2 ;; 22 ; 5 ;; 23 ; 3 ;; 24 ; 4 ;; 25 ; 3 ;; 26 ; 2 ;; 27 ; 0 ;; 28 ; 1 ;; 29 ; 1 ;; 30 ; 2 ;; 31 ; 1 ;; 32 ; 19 ;+----------------------------------------------+------------------------------++---------------------------------------------------------------------------------+; LAB Signals Sourced Out ;+--------------------------------------------------+------------------------------+; Number of Signals Sourced Out (Average = 10.45) ; Number of LABs (Total = 77) ;+--------------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 9 ;; 2 ; 4 ;; 3 ; 0 ;; 4 ; 1 ;; 5 ; 1 ;; 6 ; 1 ;; 7 ; 1 ;; 8 ; 7 ;; 9 ; 8 ;; 10 ; 5 ;; 11 ; 6 ;; 12 ; 1 ;; 13 ; 4 ;; 14 ; 6 ;; 15 ; 3 ;; 16 ; 16 ;; 17 ; 2 ;; 18 ; 1 ;; 19 ; 0 ;; 20 ; 0 ;; 21 ; 1 ;+--------------------------------------------------+------------------------------++-----------------------------------------------------------------------------+; LAB Distinct Inputs ;+----------------------------------------------+------------------------------+; Number of Distinct Inputs (Average = 17.51) ; Number of LABs (Total = 77) ;+----------------------------------------------+------------------------------+; 0 ; 0 ;; 1 ; 0 ;; 2 ; 4 ;; 3 ; 2 ;; 4 ; 3 ;; 5 ; 2 ;; 6 ; 4 ;; 7 ; 0 ;; 8 ; 2 ;; 9 ; 2 ;; 10 ; 0 ;; 11 ; 3 ;; 12 ; 4 ;; 13 ; 1 ;; 14 ; 0 ;; 15 ; 3 ;; 16 ; 1 ;; 17 ; 2 ;; 18 ; 5 ;; 19 ; 7 ;; 20 ; 1 ;; 21 ; 4 ;; 22 ; 2 ;; 23 ; 4 ;; 24 ; 5 ;; 25 ; 0 ;; 26 ; 2 ;; 27 ; 4 ;; 28 ; 2 ;; 29 ; 0 ;; 30 ; 1 ;; 31 ; 0 ;; 32 ; 1 ;; 33 ; 1 ;; 34 ; 4 ;; 35 ; 1 ;+----------------------------------------------+------------------------------++------------------------------------------+; I/O Rules Summary ;+----------------------------------+-------+; I/O Rules Statistic ; Total ;+----------------------------------+-------+; Total I/O Rules ; 31 ;; Number of I/O Rules Passed ; 4 ;; Number of I/O Rules Failed ; 0 ;; Number of I/O Rules Unchecked ; 0 ;; Number of I/O Rules Inapplicable ; 27 ;+----------------------------------+-------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Details ;+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ;; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;; Inapplicable ; IO_000032 ; I/O Properties Checks for Multiple I/Os ; I/O registers and SERDES should not be used at the same XY location. ; Critical ; No I/O Registers or Differential I/O Standard assignments found. ; I/O ; ;; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 1 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000037 ; SI Related Distance Checks ; Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000038 ; SI Related SSO Limit Checks ; Single-ended outputs and High-speed LVDS should not coexist in an I/O bank. ; High ; No High-speed LVDS found. ; I/O ; ;; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;; Inapplicable ; IO_000040 ; SI Related SSO Limit Checks ; The total drive strength of single ended outputs in a DPA bank should not exceed 120mA. ; High ; No DPA found. ; I/O ; ;+--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; I/O Rules Matrix ;+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000032 ; IO_000033 ; IO_000034 ; IO_000037 ; IO_000038 ; IO_000042 ; IO_000040 ;+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 145 ; 0 ; 0 ; 145 ; 145 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 145 ; 0 ; 0 ; 0 ; 0 ; 0 ;; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; Total Inapplicable ; 145 ; 145 ; 145 ; 145 ; 145 ; 0 ; 145 ; 145 ; 0 ; 0 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 145 ; 0 ; 145 ; 145 ; 145 ; 145 ; 145 ;; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;; in_rdy ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_rdy ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_key[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_rd_rdy ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[47] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[46] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[45] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[44] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[43] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[42] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[41] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[40] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[39] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[38] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[37] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[36] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[35] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[34] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[33] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[32] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_mac[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; out_port[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; clk ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; reset ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_wr ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_ctrl[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[63] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[62] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[61] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[60] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[59] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[58] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[57] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[56] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[55] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[54] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[53] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[52] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[51] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[50] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[49] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[48] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[47] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[46] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[45] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[44] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[43] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[42] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[41] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[40] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[39] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[38] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[37] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[36] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[35] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[34] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[33] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[32] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[31] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[30] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[29] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[28] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[27] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[26] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[25] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[24] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[23] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[22] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[21] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[20] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[19] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[18] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[17] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[16] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_rd ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;; in_data[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ;+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------++-------------------------------------------------------------------------+; Fitter Device Options ;+----------------------------------------------+--------------------------+; Option ; Setting ;+----------------------------------------------+--------------------------+; Enable user-supplied start-up clock (CLKUSR) ; Off ;; Enable device-wide reset (DEV_CLRn) ; Off ;; Enable device-wide output enable (DEV_OE) ; Off ;; Enable INIT_DONE output ; Off ;; Configuration scheme ; Passive Serial ;; Error detection CRC ; Off ;; nWS, nRS, nCS, CS ; Unreserved ;; RDYnBUSY ; Unreserved ;; Data[7..1] ; Unreserved ;; Data[0] ; As input tri-stated ;; ASDO,nCSO ; Unreserved ;; Reserve all unused pins ; As output driving ground ;; Base pin-out file on sameframe device ; Off ;+----------------------------------------------+--------------------------++------------------------------------+; Operating Settings and Conditions ;+---------------------------+--------+; Setting ; Value ;+---------------------------+--------+; Nominal Core Voltage ; 1.20 V ;+---------------------------+--------++-----------------+; Fitter Messages ;+-----------------+Info: *******************************************************************Info: Running Quartus II FitterInfo: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full VersionInfo: Processing started: Sun Jan 10 21:11:47 2010Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LB -c LBInfo: Automatically selected device EP2S15F484C3 for design LBWarning: The high junction temperature operating condition is not set. Assuming a default value of '85'.Warning: The low junction temperature operating condition is not set. Assuming a default value of '0'.Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation timeInfo: The Fitter has identified 1 logical partitions of which 0 have a previous placement to useInfo: Previous placement does not exist for 1766 of 1766 atoms in partition TopInfo: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devicesInfo: Device EP2S30F484C3 is compatibleInfo: Device EP2S60F484C3 is compatibleInfo: Device EP2S60F484C3ES is compatibleInfo: Fitter converted 1 user pins into dedicated programming pinsInfo: Pin ~DATA0~ is reserved at location E13Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.Warning: No exact pin location assignment(s) for 145 pins of 145 total pinsInfo: Pin in_rdy not assigned to an exact location on the deviceInfo: Pin out_rdy not assigned to an exact location on the deviceInfo: Pin in_key[9] not assigned to an exact location on the deviceInfo: Pin in_key[8] not assigned to an exact location on the deviceInfo: Pin in_key[7] not assigned to an exact location on the deviceInfo: Pin in_key[6] not assigned to an exact location on the deviceInfo: Pin in_key[5] not assigned to an exact location on the deviceInfo: Pin in_key[4] not assigned to an exact location on the deviceInfo: Pin in_key[3] not assigned to an exact location on the deviceInfo: Pin in_key[2] not assigned to an exact location on the deviceInfo: Pin in_key[1] not assigned to an exact location on the deviceInfo: Pin in_key[0] not assigned to an exact location on the deviceInfo: Pin out_rd_rdy not assigned to an exact location on the deviceInfo: Pin out_mac[47] not assigned to an exact location on the deviceInfo: Pin out_mac[46] not assigned to an exact location on the deviceInfo: Pin out_mac[45] not assigned to an exact location on the deviceInfo: Pin out_mac[44] not assigned to an exact location on the deviceInfo: Pin out_mac[43] not assigned to an exact location on the deviceInfo: Pin out_mac[42] not assigned to an exact location on the deviceInfo: Pin out_mac[41] not assigned to an exact location on the deviceInfo: Pin out_mac[40] not assigned to an exact location on the deviceInfo: Pin out_mac[39] not assigned to an exact location on the deviceInfo: Pin out_mac[38] not assigned to an exact location on the deviceInfo: Pin out_mac[37] not assigned to an exact location on the deviceInfo: Pin out_mac[36] not assigned to an exact location on the deviceInfo: Pin out_mac[35] not assigned to an exact location on the deviceInfo: Pin out_mac[34] not assigned to an exact location on the deviceInfo: Pin out_mac[33] not assigned to an exact location on the deviceInfo: Pin out_mac[32] not assigned to an exact location on the deviceInfo: Pin out_mac[31] not assigned to an exact location on the deviceInfo: Pin out_mac[30] not assigned to an exact location on the deviceInfo: Pin out_mac[29] not assigned to an exact location on the deviceInfo: Pin out_mac[28] not assigned to an exact location on the deviceInfo: Pin out_mac[27] not assigned to an exact location on the deviceInfo: Pin out_mac[26] not assigned to an exact location on the deviceInfo: Pin out_mac[25] not assigned to an exact location on the deviceInfo: Pin out_mac[24] not assigned to an exact location on the deviceInfo: Pin out_mac[23] not assigned to an exact location on the deviceInfo: Pin out_mac[22] not assigned to an exact location on the deviceInfo: Pin out_mac[21] not assigned to an exact location on the deviceInfo: Pin out_mac[20] not assigned to an exact location on the deviceInfo: Pin out_mac[19] not assigned to an exact location on the deviceInfo: Pin out_mac[18] not assigned to an exact location on the deviceInfo: Pin out_mac[17] not assigned to an exact location on the deviceInfo: Pin out_mac[16] not assigned to an exact location on the deviceInfo: Pin out_mac[15] not assigned to an exact location on the deviceInfo: Pin out_mac[14] not assigned to an exact location on the deviceInfo: Pin out_mac[13] not assigned to an exact location on the deviceInfo: Pin out_mac[12] not assigned to an exact location on the deviceInfo: Pin out_mac[11] not assigned to an exact location on the deviceInfo: Pin out_mac[10] not assigned to an exact location on the deviceInfo: Pin out_mac[9] not assigned to an exact location on the deviceInfo: Pin out_mac[8] not assigned to an exact location on the deviceInfo: Pin out_mac[7] not assigned to an exact location on the deviceInfo: Pin out_mac[6] not assigned to an exact location on the deviceInfo: Pin out_mac[5] not assigned to an exact location on the deviceInfo: Pin out_mac[4] not assigned to an exact location on the deviceInfo: Pin out_mac[3] not assigned to an exact location on the deviceInfo: Pin out_mac[2] not assigned to an exact location on the deviceInfo: Pin out_mac[1] not assigned to an exact location on the deviceInfo: Pin out_mac[0] not assigned to an exact location on the deviceInfo: Pin out_port[7] not assigned to an exact location on the deviceInfo: Pin out_port[6] not assigned to an exact location on the deviceInfo: Pin out_port[5] not assigned to an exact location on the deviceInfo: Pin out_port[4] not assigned to an exact location on the deviceInfo: Pin out_port[3] not assigned to an exact location on the deviceInfo: Pin out_port[2] not assigned to an exact location on the deviceInfo: Pin out_port[1] not assigned to an exact location on the deviceInfo: Pin out_port[0] not assigned to an exact location on the deviceInfo: Pin clk not assigned to an exact location on the deviceInfo: Pin reset not assigned to an exact location on the deviceInfo: Pin in_wr not assigned to an exact location on the deviceInfo: Pin in_ctrl[3] not assigned to an exact location on the deviceInfo: Pin in_ctrl[5] not assigned to an exact location on the deviceInfo: Pin in_ctrl[4] not assigned to an exact location on the deviceInfo: Pin in_ctrl[7] not assigned to an exact location on the deviceInfo: Pin in_ctrl[2] not assigned to an exact location on the deviceInfo: Pin in_ctrl[6] not assigned to an exact location on the deviceInfo: Pin in_ctrl[1] not assigned to an exact location on the deviceInfo: Pin in_ctrl[0] not assigned to an exact location on the deviceInfo: Pin in_data[63] not assigned to an exact location on the deviceInfo: Pin in_data[62] not assigned to an exact location on the deviceInfo: Pin in_data[61] not assigned to an exact location on the deviceInfo: Pin in_data[60] not assigned to an exact location on the deviceInfo: Pin in_data[59] not assigned to an exact location on the deviceInfo: Pin in_data[58] not assigned to an exact location on the deviceInfo: Pin in_data[57] not assigned to an exact location on the deviceInfo: Pin in_data[56] not assigned to an exact location on the deviceInfo: Pin in_data[55] not assigned to an exact location on the deviceInfo: Pin in_data[54] not assigned to an exact location on the deviceInfo: Pin in_data[53] not assigned to an exact location on the deviceInfo: Pin in_data[52] not assigned to an exact location on the deviceInfo: Pin in_data[51] not assigned to an exact location on the deviceInfo: Pin in_data[50] not assigned to an exact location on the deviceInfo: Pin in_data[49] not assigned to an exact location on the deviceInfo: Pin in_data[48] not assigned to an exact location on the deviceInfo: Pin in_data[47] not assigned to an exact location on the deviceInfo: Pin in_data[46] not assigned to an exact location on the deviceInfo: Pin in_data[45] not assigned to an exact location on the deviceInfo: Pin in_data[44] not assigned to an exact location on the deviceInfo: Pin in_data[43] not assigned to an exact location on the deviceInfo: Pin in_data[42] not assigned to an exact location on the deviceInfo: Pin in_data[41] not assigned to an exact location on the deviceInfo: Pin in_data[40] not assigned to an exact location on the deviceInfo: Pin in_data[39] not assigned to an exact location on the deviceInfo: Pin in_data[38] not assigned to an exact location on the deviceInfo: Pin in_data[37] not assigned to an exact location on the deviceInfo: Pin in_data[36] not assigned to an exact location on the deviceInfo: Pin in_data[35] not assigned to an exact location on the deviceInfo: Pin in_data[34] not assigned to an exact location on the deviceInfo: Pin in_data[33] not assigned to an exact location on the deviceInfo: Pin in_data[32] not assigned to an exact location on the deviceInfo: Pin in_data[31] not assigned to an exact location on the deviceInfo: Pin in_data[30] not assigned to an exact location on the deviceInfo: Pin in_data[29] not assigned to an exact location on the deviceInfo: Pin in_data[28] not assigned to an exact location on the deviceInfo: Pin in_data[27] not assigned to an exact location on the deviceInfo: Pin in_data[26] not assigned to an exact location on the deviceInfo: Pin in_data[25] not assigned to an exact location on the deviceInfo: Pin in_data[24] not assigned to an exact location on the deviceInfo: Pin in_data[23] not assigned to an exact location on the deviceInfo: Pin in_data[22] not assigned to an exact location on the deviceInfo: Pin in_data[21] not assigned to an exact location on the deviceInfo: Pin in_data[20] not assigned to an exact location on the deviceInfo: Pin in_data[19] not assigned to an exact location on the deviceInfo: Pin in_data[18] not assigned to an exact location on the deviceInfo: Pin in_data[17] not assigned to an exact location on the deviceInfo: Pin in_data[16] not assigned to an exact location on the deviceInfo: Pin in_data[7] not assigned to an exact location on the deviceInfo: Pin in_data[6] not assigned to an exact location on the deviceInfo: Pin in_data[5] not assigned to an exact location on the deviceInfo: Pin in_data[4] not assigned to an exact location on the deviceInfo: Pin in_data[3] not assigned to an exact location on the deviceInfo: Pin in_data[2] not assigned to an exact location on the deviceInfo: Pin in_data[1] not assigned to an exact location on the deviceInfo: Pin in_data[0] not assigned to an exact location on the deviceInfo: Pin in_rd not assigned to an exact location on the deviceInfo: Pin in_data[13] not assigned to an exact location on the deviceInfo: Pin in_data[15] not assigned to an exact location on the deviceInfo: Pin in_data[14] not assigned to an exact location on the deviceInfo: Pin in_data[12] not assigned to an exact location on the deviceInfo: Pin in_data[11] not assigned to an exact location on the deviceInfo: Pin in_data[10] not assigned to an exact location on the deviceInfo: Pin in_data[9] not assigned to an exact location on the deviceInfo: Pin in_data[8] not assigned to an exact location on the deviceInfo: Fitter is using the Classic Timing AnalyzerInfo: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirementsInfo: Automatically promoted node clk (placed in PIN N20 (CLK3p, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3Info: Automatically promoted node reset (placed in PIN M21 (CLK1p, Input))Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1Info: Following destination nodes may be non-global or may not use global or regional clocksInfo: Destination node manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[0]Info: Destination node manager:inst|table:table_Inst|small_fifo:small_fifo_Inst|wr_ptr[6]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[0]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[1]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[2]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[3]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|valid_address:valid_address_Inst|small_fifo:remove_command_Inst|wr_ptr[4]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[0]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[1]Info: Destination node manager:inst|table:table_Inst|mac_ram_table:ram_Inst|small_fifo:WRITE_command_Inst|wr_ptr[2]Info: Non-global destination nodes limited to 10 nodesInfo: Starting register packingInfo: Finished register packing: elapsed time is 00:00:02Extra Info: No registers were packed into other blocksInfo: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placementInfo: Number of I/O pins in group: 143 (unused VREF, 3.30 VCCIO, 85 input, 58 output, 0 bidirectional)Info: I/O standards used: 3.3-V LVTTL.Info: I/O bank details before I/O pin placementInfo: Statistics of I/O banksInfo: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins availableInfo: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins availableInfo: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins availableInfo: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins availableInfo: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins availableInfo: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins availableInfo: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins availableInfo: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins availableInfo: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins availableInfo: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins availableInfo: Fitter placement preparation operations beginningInfo: Fitter placement preparation operations ending: elapsed time is 00:00:02Info: Fitter placement operations beginningInfo: Fitter placement was successfulInfo: Fitter placement operations ending: elapsed time is 00:00:06Info: Estimated most critical path is memory to memory delay of 4.941 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X8_Y10; Fanout = 1; MEM Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9'Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X8_Y10; Fanout = 2; MEM Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[0]'Info: 3: + IC(0.631 ns) + CELL(0.357 ns) = 2.838 ns; Loc. = LAB_X13_Y12; Fanout = 32; COMB Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26'Info: 4: + IC(0.023 ns) + CELL(0.378 ns) = 3.239 ns; Loc. = LAB_X13_Y12; Fanout = 1; COMB Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector19~26'Info: 5: + IC(0.348 ns) + CELL(0.053 ns) = 3.640 ns; Loc. = LAB_X13_Y12; Fanout = 3; COMB Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector19~24'Info: 6: + IC(0.044 ns) + CELL(0.357 ns) = 4.041 ns; Loc. = LAB_X13_Y12; Fanout = 2; COMB Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector19~25'Info: 7: + IC(0.797 ns) + CELL(0.103 ns) = 4.941 ns; Loc. = M4K_X8_Y10; Fanout = 0; MEM Node = 'manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a1~porta_address_reg9'Info: Total cell delay = 3.098 ns ( 62.70 % )Info: Total interconnect delay = 1.843 ns ( 37.30 % )Info: Fitter routing operations beginningInfo: Average interconnect usage is 4% of the available device resourcesInfo: Peak interconnect usage is 10% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13Info: Fitter routing operations ending: elapsed time is 00:00:11Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.Info: Optimizations that may affect the design's routability were skippedInfo: Optimizations that may affect the design's timing were skippedInfo: Started post-fitting delay annotationWarning: Found 58 output pins without output pin load capacitance assignmentInfo: Pin "in_rdy" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_rd_rdy" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[47]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[46]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[45]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[44]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[43]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[42]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[41]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[40]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[39]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[38]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[37]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[36]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[35]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[34]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[33]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[32]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[31]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[30]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[29]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[28]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[27]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[26]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[25]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[24]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[23]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[22]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[21]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[20]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[19]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[18]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[17]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[16]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_mac[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Pin "out_port[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysisInfo: Delay annotation completed successfullyWarning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting resultsInfo: Pin in_rdy has GND driving its datain portWarning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.Info: Generated suppressed messages file C:/Documents and Settings/Shadi/Desktop/LB/LB.fit.smsgInfo: Quartus II Fitter was successful. 0 errors, 6 warningsInfo: Allocated 201 megabytes of memory during processingInfo: Processing ended: Sun Jan 10 21:13:02 2010Info: Elapsed time: 00:01:15+----------------------------+; Fitter Suppressed Messages ;+----------------------------+The suppressed messages can be found in C:/Documents and Settings/Shadi/Desktop/LB/LB.fit.smsg.