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[/] [loadbalancer/] [trunk/] [db/] [LB.tan.qmsg] - Rev 2
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 21:13:49 2010 " "Info: Processing started: Sun Jan 10 21:13:49 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off LB -c LB --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LB -c LB --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}{ "Info" "ITDB_FULL_SLACK_RESULT" "clk memory manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~portb_address_reg9 memory manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~porta_address_reg6 2.784 ns " "Info: Slack time is 2.784 ns for clock \"clk\" between source memory \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~portb_address_reg9\" and destination memory \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~porta_address_reg6\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "191.72 MHz 5.216 ns " "Info: Fmax is 191.72 MHz (period= 5.216 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.856 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 7.856 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "8.000 ns + " "Info: + Setup relationship between source and destination is 8.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 8.000 ns " "Info: + Latch edge is 8.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.014 ns + Largest " "Info: + Largest clock skew is 0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.348 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk\" to destination memory is 2.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'"0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.481 ns) 2.348 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~porta_address_reg6 3 MEM M4K_X8_Y10 0 " "Info: 3: + IC(0.670 ns) + CELL(0.481 ns) = 2.348 ns; Loc. = M4K_X8_Y10; Fanout = 0; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~porta_address_reg6'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.151 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 37 2 0 } } }0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.335 ns ( 56.86 % ) " "Info: Total cell delay = 1.335 ns ( 56.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 43.14 % ) " "Info: Total interconnect delay = 1.013 ns ( 43.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.334 ns - Longest memory " "Info: - Longest clock path from clock \"clk\" to source memory is 2.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.467 ns) 2.334 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~portb_address_reg9 3 MEM M4K_X8_Y10 2 " "Info: 3: + IC(0.670 ns) + CELL(0.467 ns) = 2.334 ns; Loc. = M4K_X8_Y10; Fanout = 2; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~portb_address_reg9'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.137 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 } "NODE_NAME" } } { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.321 ns ( 56.60 % ) " "Info: Total cell delay = 1.321 ns ( 56.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 43.40 % ) " "Info: Total interconnect delay = 1.013 ns ( 43.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns - " "Info: - Micro clock to output delay of source is 0.136 ns" { } { { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 37 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns - " "Info: - Micro setup delay of destination is 0.022 ns" { } { { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 37 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } {{ "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.072 ns - Longest memory memory " "Info: - Longest memory to memory delay is 5.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~portb_address_reg9 1 MEM M4K_X8_Y10 2 " "Info: 1: + IC(0.000ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X8_Y10; Fanout = 2; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~portb_address_reg9'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 } "NODE_NAME" } } { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.850 ns) 1.850 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|q_b\[1\] 2 MEM M4K_X8_Y10 16 " "Info: 2: + IC(0.000 ns) + CELL(1.850 ns) = 1.850 ns; Loc. = M4K_X8_Y10; Fanout = 16; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|q_b\[1\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.850 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[1] } "NODE_NAME" } } { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 33 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.007 ns) + CELL(0.228 ns) 3.085 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|we_av~26 3 COMB LCCOMB_X13_Y12_N24 32 " "Info: 3: + IC(1.007 ns) + CELL(0.228 ns) = 3.085 ns; Loc. = LCCOMB_X13_Y12_N24; Fanout = 32; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|we_av~26'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.235 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[1] manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 150 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.053 ns) 3.954 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Selector22~24 4 COMB LCCOMB_X15_Y11_N30 1 " "Info: 4: + IC(0.816 ns) + CELL(0.053 ns) = 3.954 ns; Loc. = LCCOMB_X15_Y11_N30; Fanout = 1; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Selector22~24'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector22~24 } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 382 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.103 ns) 5.072 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~porta_address_reg6 5 MEM M4K_X8_Y10 0 " "Info: 5: + IC(1.015 ns) + CELL(0.103 ns) = 5.072 ns; Loc. = M4K_X8_Y10; Fanout = 0; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:Aging_Valid_256x48_Inst\|altsyncram:ram_rtl_3\|altsyncram_pvi1:auto_generated\|ram_block1a0~porta_address_reg6'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.118 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector22~24 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "db/altsyncram_pvi1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_pvi1.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.234 ns ( 44.05 % ) " "Info: Total cell delay = 2.234 ns ( 44.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.838 ns ( 55.95 % ) " "Info: Total interconnect delay = 2.838 ns ( 55.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.072 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[1] manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector22~24 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.072 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[1] {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector22~24 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 {} } { 0.000ns 0.000ns 1.007ns 0.816ns 1.015ns } { 0.000ns 1.850ns 0.228ns 0.053ns 0.103ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.348 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.348 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.334 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.334 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.072 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[1] manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector22~24 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.072 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~portb_address_reg9 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|q_b[1] {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|we_av~26 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Selector22~24 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:Aging_Valid_256x48_Inst|altsyncram:ram_rtl_3|altsyncram_pvi1:auto_generated|ram_block1a0~porta_address_reg6 {} } { 0.000ns 0.000ns 1.007ns 0.816ns 1.015ns } { 0.000ns 1.850ns 0.228ns 0.053ns 0.103ns } "" } } } 0 0 "Slack time is%6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[2\] register manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~77 354 ps " "Info: Minimum slack time is 354 ps for clock \"clk\" between source register \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[2\]\" and destination register \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~77\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.409 ns + Shortest register register " "Info: + Shortest register to register delay is 0.409 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[2\] 1 REG LCFF_X17_Y12_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y12_N5; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[2\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.201 ns) + CELL(0.053 ns) 0.254 ns manager:inst\|table:table_Inst\|Selector13~8 2 COMB LCCOMB_X17_Y12_N22 30 " "Info: 2: + IC(0.201 ns) + CELL(0.053 ns) = 0.254 ns; Loc. = LCCOMB_X17_Y12_N22; Fanout = 30; COMB Node = 'manager:inst\|table:table_Inst\|Selector13~8'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.254 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] manager:inst|table:table_Inst|Selector13~8 } "NODE_NAME" } } { "TABLE/table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/table.vhd" 189 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.409 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~77 3 REG LCFF_X17_Y12_N23 3 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.409 ns; Loc. = LCFF_X17_Y12_N23; Fanout = 3; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~77'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { manager:inst|table:table_Inst|Selector13~8 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!;%5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.208 ns ( 50.86 % ) " "Info: Total cell delay = 0.208 ns ( 50.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.201 ns ( 49.14 % ) " "Info: Total interconnect delay = 0.201 ns ( 49.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.409 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] manager:inst|table:table_Inst|Selector13~8 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.409 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] {} manager:inst|table:table_Inst|Selector13~8 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 {} } { 0.000ns 0.201ns 0.000ns } { 0.000ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.055 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.055 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!"0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.468 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~77 3 REG LCFF_X17_Y12_N23 3 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X17_Y12_N23; Fanout = 3; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|ram~77'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" {Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.468 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.653 ns) + CELL(0.618 ns) 2.468 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[2\] 3 REG LCFF_X17_Y12_N5 1 " "Info: 3: + IC(0.653 ns) + CELL(0.618 ns) = 2.468 ns; Loc. = LCFF_X17_Y12_N5; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[2\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.271 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.64 % ) " "Info: Total cell delay = 1.472 ns ( 59.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 40.36 % ) " "Info: Total interconnect delay = 0.996 ns ( 40.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" { } { { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 00 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 35 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.409 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] manager:inst|table:table_Inst|Selector13~8 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.409 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] {} manager:inst|table:table_Inst|Selector13~8 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 {} } { 0.000ns 0.201ns 0.000ns } { 0.000ns 0.053ns 0.155ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|ram~77 {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.468 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.468 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[2] {} } { 0.000ns 0.000ns 0.343ns 0.653ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}{ "Info" "ITDB_TSU_RESULT" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_2\|altsyncram_b3j1:auto_generated\|ram_block1a18~portb_address_reg9 reset clk 6.345 ns memory " "Info: tsu for memory \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_2\|altsyncram_b3j1:auto_generated\|ram_block1a18~portb_address_reg9\" (data pin = \"reset\", clock pin = \"clk\") is 6.345 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.664 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.664 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns reset 1 PIN PIN_M21 214 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 214; PIN Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.096 ns) + CELL(0.346 ns) 6.306 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|cnt1~234 2 COMB LCCOMB_X19_Y12_N28 14 " "Info: 2: + IC(5.096 ns) + CELL(0.346 ns) = 6.306 ns; Loc. = LCCOMB_X19_Y12_N28; Fanout = 14; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|cnt1~234'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.442 ns" { reset manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 254 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.257 ns) + CELL(0.101 ns) 8.664 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_2\|altsyncram_b3j1:auto_generated\|ram_block1a18~portb_address_reg9 3 MEM M4K_X32_Y3 4 " "Info: 3: + IC(2.257 ns) + CELL(0.101 ns) = 8.664 ns; Loc. = M4K_X32_Y3; Fanout = 4; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_2\|altsyncram_b3j1:auto_generated\|ram_block1a18~portb_address_reg9'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.358 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 } "NODE_NAME" } } { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 577 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!;Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.311 ns ( 15.13 % ) " "Info: Total cell delay = 1.311 ns ( 15.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.353 ns ( 84.87 % ) " "Info: Total interconnect delay = 7.353 ns ( 84.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.664 ns" { reset manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.664 ns" { reset {} reset~combout {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 {} } { 0.000ns 0.000ns 5.096ns 2.257ns } { 0.000ns 0.864ns 0.346ns 0.101ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" { } { { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 577 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.341 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 2.341 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.467 ns) 2.341 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_2\|altsyncram_b3j1:auto_generated\|ram_block1a18~portb_address_reg9 3 MEM M4K_X32_Y3 4 " "Info: 3: + IC(0.677 ns) + CELL(0.467 ns) = 2.341 ns; Loc. = M4K_X32_Y3; Fanout = 4; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_2\|altsyncram_b3j1:auto_generated\|ram_block1a18~portb_address_reg9'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.144 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 } "NODE_NAME" } } { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 577 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.321 ns ( 56.43 % ) " "Info: Total cell delay = 1.321 ns ( 56.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.020 ns ( 43.57 % ) " "Info: Total interconnect delay = 1.020 ns ( 43.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.677ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.664 ns" { reset manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.664 ns" { reset {} reset~combout {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 {} } { 0.000ns 0.000ns 5.096ns 2.257ns } { 0.000ns 0.864ns 0.346ns 0.101ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.341 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.341 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_2|altsyncram_b3j1:auto_generated|ram_block1a18~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.677ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}{ "Info" "ITDB_FULL_TCO_RESULT" "clk out_mac\[8\] manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|q\[16\] 6.579 ns register " "Info: tco from clock \"clk\" to destination pin \"out_mac\[8\]\" through register \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|q\[16\]\" is 6.579 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.470 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.470 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. =%6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.655 ns) + CELL(0.618 ns) 2.470 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|q\[16\] 3 REG LCFF_X21_Y8_N29 1 " "Info: 3: + IC(0.655 ns) + CELL(0.618 ns) = 2.470 ns; Loc. = LCFF_X21_Y8_N29; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|q\[16\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.273 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] } "NODE_NAME" } } { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.60 % ) " "Info: Total cell delay = 1.472 ns ( 59.60 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 40.40 % ) " "Info: Total interconnect delay = 0.998 ns ( 40.40 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.470 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.470 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] {} } { 0.000ns 0.000ns 0.343ns 0.655ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.015 ns + Longest register pin " "Info: + Longest register to pin delay is 4.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|q\[16\] 1 REG LCFF_X21_Y8_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N29; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_Inst\|q\[16\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] } "NODE_NAME" } } { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.063 ns) + CELL(1.952 ns) 4.015 ns out_mac\[8\] 2 PIN PIN_E11 0 " "Info: 2: + IC(2.063 ns) + CELL(1.952 ns) = 4.015 ns; Loc. = PIN_E11; Fanout = 0; PIN Node = 'out_mac\[8\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.015 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] out_mac[8] } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 408 808 984 424 "out_mac\[47..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.952 ns ( 48.62 % ) " "Info: Total cell delay = 1.952 ns ( 48.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.063 ns ( 51.38 % ) " "Info: Total interconnect delay = 2.063 ns ( 51.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.015 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] out_mac[8] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.015 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] {} out_mac[8] {} } { 0.000ns 2.063ns } { 0.000ns 1.952ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.470 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.470 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] {} } { 0.000ns 0.000ns 0.343ns 0.655ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.015 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] out_mac[8] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.015 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_Inst|q[16] {} out_mac[8] {} } { 0.000ns 2.063ns } { 0.000ns 1.952ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}{ "Info" "ITDB_TH_RESULT" "manager:inst\|mac_weight\[6\] in_data\[14\] clk -2.272 ns register " "Info: th for register \"manager:inst\|mac_weight\[6\]\" (data pin = \"in_data\[14\]\", clock pin = \"clk\") is -2.272 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.477 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.477 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2162 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2162; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 520 448 616 536 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.662 ns) + CELL(0.618 ns) 2.477 ns manager:inst\|mac_weight\[6\] 3 REG LCFF_X26_Y17_N23 2 " "Info: 3: + IC(0.662 ns) + CELL(0.618 ns) = 2.477 ns; Loc. = LCFF_X26_Y17_N23; Fanout = 2; REG Node = 'manager:inst\|mac_weight\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { clk~clkctrl manager:inst|mac_weight[6] } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 260 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.43 % ) " "Info: Total cell delay = 1.472 ns ( 59.43 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.005 ns ( 40.57 % ) " "Info: Total interconnect delay = 1.005 ns ( 40.57 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.477 ns" { clk clk~clkctrl manager:inst|mac_weight[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.477 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|mac_weight[6] {} } { 0.000ns 0.000ns 0.343ns 0.662ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 00 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 260 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.898 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.898 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns in_data\[14\] 1 PIN PIN_L8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_L8; Fanout = 1; PIN Node = 'in_data\[14\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { in_data[14] } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 392 448 616 408 "in_data\[63..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.910 ns) + CELL(0.053 ns) 4.743 ns manager:inst\|mac_weight\[6\]~feeder 2 COMB LCCOMB_X26_Y17_N22 1 " "Info: 2: + IC(3.910 ns) + CELL(0.053 ns) = 4.743 ns; Loc. = LCCOMB_X26_Y17_N22; Fanout = 1; COMB Node = 'manager:inst\|mac_weight\[6\]~feeder'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.963 ns" { in_data[14] manager:inst|mac_weight[6]~feeder } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 260 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.898 ns manager:inst\|mac_weight\[6\] 3 REG LCFF_X26_Y17_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.898 ns; Loc. = LCFF_X26_Y17_N23; Fanout = 2; REG Node = 'manager:inst\|mac_weight\[6\]'" { }{ { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { manager:inst|mac_weight[6]~feeder manager:inst|mac_weight[6] } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 260 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.988 ns ( 20.17 % ) " "Info: Total cell delay = 0.988 ns ( 20.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.910 ns ( 79.83 % ) " "Info: Total interconnect delay = 3.910 ns ( 79.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.898 ns" { in_data[14] manager:inst|mac_weight[6]~feeder manager:inst|mac_weight[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.898 ns" { in_data[14] {} in_data[14]~combout {} manager:inst|mac_weight[6]~feeder {} manager:inst|mac_weight[6] {} } { 0.000ns 0.000ns 3.910ns 0.000ns } { 0.000ns 0.780ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.477 ns" { clk clk~clkctrl manager:inst|mac_weight[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.477 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|mac_weight[6] {} } { 0.000ns 0.000ns 0.343ns 0.662ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.898 ns" { in_data[14] manager:inst|mac_weight[6]~feeder manager:inst|mac_weight[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.898 ns" { in_data[14] {} in_data[14]~combout {} manager:inst|mac_weight[6]~feeder {} manager:inst|mac_weight[6] {} } { 0.000ns 0.000ns 3.910ns 0.000ns } { 0.000ns 0.780ns 0.053ns 0.155ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0}{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Allocated 127 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 21:13:58 2010 " "Info: Processing ended: Sun Jan 10 21:13:58 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}