URL
https://opencores.org/ocsvn/loadbalancer/loadbalancer/trunk
Subversion Repositories loadbalancer
[/] [loadbalancer/] [trunk/] [db/] [prev_cmp_LB.tan.qmsg] - Rev 2
Compare with Previous | Blame | View Log
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jan 10 18:12:51 2010 " "Info: Processing started: Sun Jan 10 18:12:51 2010" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off LB -c LB --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LB -c LB --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|q\[40\] register manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[9\] 2.678 ns " "Info: Slack time is 2.678 ns for clock \"clk\" between source register \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|q\[40\]\" and destination register \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[9\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "187.9 MHz 5.322 ns " "Info: Fmax is 187.9 MHz (period= 5.322 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "7.838 ns + Largest register register " "Info: + Largest register to register requirement is 7.838 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "8.000 ns + " "Info: + Setup relationship between source and destination is 8.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 8.000 ns " "Info: + Latch edge is 8.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.022 ns + Largest " "Info: + Largest clock skew is 0.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.485 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.485 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: +%1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.670 ns) + CELL(0.618 ns) 2.485 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[9\] 3 REG LCFF_X25_Y10_N19 1 " "Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.485 ns; Loc. = LCFF_X25_Y10_N19; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[9\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.288 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.24 % ) " "Info: Total cell delay = 1.472 ns ( 59.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.013 ns ( 40.76 % ) " "Info: Total interconnect delay = 1.013 ns ( 40.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.463 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.648 ns) + CELL(0.618 ns) 2.463 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|q\[40\] 3 REG LCFF_X18_Y15_N13 1 " "Info: 3: + IC(0.648 ns) + CELL(0.618 ns) = 2.463 ns; Loc. =LCFF_X18_Y15_N13; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|q\[40\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.266 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] } "NODE_NAME" } } { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.76 % ) " "Info: Total cell delay = 1.472 ns ( 59.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 40.24 % ) " "Info: Total interconnect delay = 0.991 ns ( 40.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" ""{ Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" { } { { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns - " "Info: - Micro setup delay of destination is 0.090 ns" { } { { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.485 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.160 ns - Longest register register " "Info: - Longest register to register delay is 5.160 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|q\[40\] 1 REG LCFF_X18_Y15_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y15_N13; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|q\[40\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] } "NODE_NAME" } } { "TABLE/ram_256x48.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/ram_256x48.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.357 ns) + CELL(0.378 ns) 0.735 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~331 2 COMB LCCOMB_X17_Y15_N12 1 " "Info: 2: + IC(0.357 ns) + CELL(0.378 ns) = 0.735 ns; Loc. = LCCOMB_X17_Y15_N12; Fanout = 1; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~331'" { } { {"d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~331 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.378 ns) 1.950 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~323 3 COMB LCCOMB_X15_Y11_N20 1 " "Info: 3: + IC(0.837 ns) + CELL(0.378 ns) = 1.950 ns; Loc. = LCCOMB_X15_Y11_N20; Fanout = 1; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~323'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.215 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~331 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~323 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.579 ns) + CELL(0.366 ns) 2.895 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~327 4 COMB LCCOMB_X19_Y11_N30 1 " "Info: 4: + IC(0.579 ns) + CELL(0.366 ns) = 2.895 ns; Loc. = LCCOMB_X19_Y11_N30; Fanout = 1; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~327'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.945 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~323 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~327 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.207 ns) + CELL(0.053 ns) 3.155 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~328 5 COMB LCCOMB_X19_Y11_N26 4 " "Info: 5: + IC(0.207 ns) + CELL(0.053 ns) = 3.155 ns; Loc. = LCCOMB_X19_Y11_N26; Fanout = 4; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|Equal0~328'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.260 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~327 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~328 } "NODE_NAME" } } { "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.227 ns) + CELL(0.053 ns) 3.435 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[0\]~1083 6 COMB LCCOMB_X19_Y11_N8 10 " "Info: 6: + IC(0.227 ns) + CELL(0.053 ns) = 3.435 ns; Loc. = LCCOMB_X19_Y11_N8; Fanout = 10; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[0\]~1083'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.280 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~328 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.979 ns) + CELL(0.746 ns) 5.160 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[9\] 7 REG LCFF_X25_Y10_N19 1 " "Info: 7: + IC(0.979 ns) + CELL(0.746 ns) = 5.160 ns; Loc. = LCFF_X25_Y10_N19; Fanout = 1; REG Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|match_address\[9\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.725 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 201 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.974 ns ( 38.26 % ) " "Info: Total cell delay = 1.974 ns ( 38.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.186 ns ( 61.74 % ) " "Info: Total interconnect delay = 3.186 ns ( 61.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.160 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~331 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~323 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~327 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~328 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.160 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~331 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~323 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~327 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~328 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] {} } { 0.000ns 0.357ns 0.837ns 0.579ns 0.207ns 0.227ns 0.979ns } { 0.000ns 0.378ns 0.378ns 0.366ns 0.053ns 0.053ns 0.746ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.485 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.485ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] {} } { 0.000ns 0.000ns 0.343ns 0.670ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.463 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.463 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] {} } { 0.000ns 0.000ns 0.343ns 0.648ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.160 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~331 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~323 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~327 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~328 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.160 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|q[40] {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~331 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~323 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~327 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|Equal0~328 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[0]~1083 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|match_address[9] {} } { 0.000ns 0.357ns 0.837ns 0.579ns 0.207ns 0.227ns 0.979ns } { 0.000ns 0.378ns 0.378ns 0.366ns 0.053ns 0.053ns 0.746ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register manager:inst\|state.in_module_hdrs register manager:inst\|state.in_module_hdrs 341 ps " "Info: Minimum slack time is 341 ps for clock \"clk\" between source register \"manager:inst\|state.in_module_hdrs\" and destination register \"manager:inst\|state.in_module_hdrs\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.396 ns + Shortest register register " "Info: + Shortest register to register delay is 0.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns manager:inst\|state.in_module_hdrs 1 REG LCFF_X18_Y14_N15 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y14_N15; Fanout = 11; REG Node = 'manager:inst\|state.in_module_hdrs'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85-1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.241 ns) 0.241 ns manager:inst\|state.in_module_hdrs~238 2 COMB LCCOMB_X18_Y14_N14 1 " "Info: 2: + IC(0.000 ns) + CELL(0.241 ns) = 0.241 ns; Loc. = LCCOMB_X18_Y14_N14; Fanout = 1; COMB Node = 'manager:inst\|state.in_module_hdrs~238'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.241 ns" { manager:inst|state.in_module_hdrs manager:inst|state.in_module_hdrs~238 } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.396 ns manager:inst\|state.in_module_hdrs 3 REG LCFF_X18_Y14_N15 11 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.396 ns; Loc. = LCFF_X18_Y14_N15; Fanout = 11; REG Node = 'manager:inst\|state.in_module_hdrs'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { manager:inst|state.in_module_hdrs~238 manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.396 ns ( 100.00 % ) " "Info: Total cell delay = 0.396 ns ( 100.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { manager:inst|state.in_module_hdrs manager:inst|state.in_module_hdrs~238 manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.396 ns" { manager:inst|state.in_module_hdrs {} manager:inst|state.in_module_hdrs~238 {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.241ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.055 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.055 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "DestinationSetup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 8.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"clk\" is 8.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.466 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.466 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.651 ns) + CELL(0.618 ns) 2.466 ns manager:inst\|state.in_module_hdrs 3 REG LCFF_X18_Y14_N15 11 " "Info: 3: + IC(0.651 ns) + CELL(0.618 ns) = 2.466 ns; Loc. = LCFF_X18_Y14_N15; Fanout = 11; REG Node = 'manager:inst\|state.in_module_hdrs'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.269 ns" { clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.69 % ) " "Info: Total cell delay = 1.472 ns ( 59.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 40.31 % ) " "Info: Total interconnect delay = 0.994 ns ( 40.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.466 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.466 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.651 ns) + CELL(0.618 ns) 2.466 ns manager:inst\|state.in_module_hdrs 3 REG LCFF_X18_Y14_N15 11 " "Info: 3: + IC(0.651 ns) + CELL(0.618 ns) = 2.466 ns; Loc. = LCFF_X18_Y14_N15; Fanout = 11; REG Node = 'manager:inst\|state.in_module_hdrs'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.269 ns" { clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.69 % ) " "Info: Total cell delay = 1.472 ns ( 59.69 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.994 ns ( 40.31 % ) " "Info: Total interconnect delay = 0.994 ns ( 40.31 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns - " "Info: - Micro clock to output delay of source is 0.094 ns" { } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" { } { { "TABLE/manager.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/manager.vhd" 85 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.396 ns" { manager:inst|state.in_module_hdrs manager:inst|state.in_module_hdrs~238 manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.396 ns" { manager:inst|state.in_module_hdrs {} manager:inst|state.in_module_hdrs~238 {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.241ns 0.155ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.466 ns" { clk clk~clkctrl manager:inst|state.in_module_hdrs } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.466 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|state.in_module_hdrs {} } { 0.000ns 0.000ns 0.343ns 0.651ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}{ "Info" "ITDB_TSU_RESULT" "manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_3\|altsyncram_b3j1:auto_generated\|ram_block1a19~portb_address_reg9 reset clk 6.009 ns memory " "Info: tsu for memory \"manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_3\|altsyncram_b3j1:auto_generated\|ram_block1a19~portb_address_reg9\" (data pin = \"reset\", clock pin = \"clk\") is 6.009 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.315 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.315 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns reset 1 PIN PIN_M21 228 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 228; PIN Node = 'reset'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 488 448 616 504 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.640 ns) + CELL(0.366 ns) 5.870 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|cnt1~234 2 COMB LCCOMB_X23_Y10_N24 14 " "Info: 2: + IC(4.640 ns) + CELL(0.366 ns) = 5.870 ns; Loc. = LCCOMB_X23_Y10_N24; Fanout = 14; COMB Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|cnt1~234'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.006 ns" { reset manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 } "NODE_NAME" } } { "TABLE/mac_ram_table.vhd" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/TABLE/mac_ram_table.vhd" 254 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.344 ns) + CELL(0.101 ns) 8.315 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_3\|altsyncram_b3j1:auto_generated\|ram_block1a19~portb_address_reg9 3 MEM M4K_X8_Y16 4 " "Info: 3: + IC(2.344 ns) + CELL(0.101 ns) = 8.315 ns; Loc. = M4K_X8_Y16; Fanout = 4; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_3\|altsyncram_b3j1:auto_generated\|ram_block1a19~portb_address_reg9'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 } "NODE_NAME" } } { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 607 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!;Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns ( 16.01 % ) " "Info: Total cell delay = 1.331 ns ( 16.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.984 ns ( 83.99 % ) " "Info: Total interconnect delay = 6.984 ns ( 83.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.315 ns" { reset manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.315 ns" { reset {} reset~combout {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 {} } { 0.000ns 0.000ns 4.640ns 2.344ns } { 0.000ns 0.864ns 0.366ns 0.101ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" { } { { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 607 2 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.328 ns - Shortest memory " "Info: - Shortest clock path from clock \"clk\" to destination memory is 2.328 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.664 ns) + CELL(0.467 ns) 2.328 ns manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_3\|altsyncram_b3j1:auto_generated\|ram_block1a19~portb_address_reg9 3 MEM M4K_X8_Y16 4 " "Info: 3: + IC(0.664 ns) + CELL(0.467 ns) = 2.328 ns; Loc. = M4K_X8_Y16; Fanout = 4; MEM Node = 'manager:inst\|table:table_Inst\|mac_ram_table:ram_Inst\|ram_256x48:ram_256x48_search_Inst\|altsyncram:ram_rtl_3\|altsyncram_b3j1:auto_generated\|ram_block1a19~portb_address_reg9'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.131 ns" { clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 } "NODE_NAME" } } { "db/altsyncram_b3j1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_b3j1.tdf" 607 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.321 ns ( 56.74 % ) " "Info: Total cell delay = 1.321 ns ( 56.74 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.007 ns ( 43.26 % ) " "Info: Total interconnect delay = 1.007 ns ( 43.26 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.328 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.328 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.315 ns" { reset manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.315 ns" { reset {} reset~combout {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|cnt1~234 {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 {} } { 0.000ns 0.000ns 4.640ns 2.344ns } { 0.000ns 0.864ns 0.366ns 0.101ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.328 ns" { clk clk~clkctrl manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.328 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|table:table_Inst|mac_ram_table:ram_Inst|ram_256x48:ram_256x48_search_Inst|altsyncram:ram_rtl_3|altsyncram_b3j1:auto_generated|ram_block1a19~portb_address_reg9 {} } { 0.000ns 0.000ns 0.343ns 0.664ns } { 0.000ns 0.854ns 0.000ns 0.467ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}{ "Info" "ITDB_FULL_TCO_RESULT" "clk in_rdy manager:inst\|small_fifo:small_fifo_Inst\|depth\[0\] 6.604 ns register " "Info: tco from clock \"clk\" to destination pin \"in_rdy\" through register \"manager:inst\|small_fifo:small_fifo_Inst\|depth\[0\]\" is 6.604 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.482 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.482 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.667 ns) + CELL(0.618 ns) 2.482 ns manager:inst\|small_fifo:small_fifo_Inst\|depth\[0\] 3 REG LCFF_X22_Y14_N23 4 " "Info: 3: + IC(0.667 ns) + CELL(0.618 ns) = 2.482 ns; Loc. = LCFF_X22_Y14_N23; Fanout = 4; REG Node = 'manager:inst\|small_fifo:small_fifo_Inst\|depth\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.285 ns" { clk~clkctrl manager:inst|small_fifo:small_fifo_Inst|depth[0] } "NODE_NAME" } } { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.31 % ) " "Info: Total cell delay = 1.472 ns ( 59.31 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.010 ns ( 40.69 % ) " "Info: Total interconnect delay = 1.010 ns ( 40.69 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { clk clk~clkctrl manager:inst|small_fifo:small_fifo_Inst|depth[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|small_fifo:small_fifo_Inst|depth[0] {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 56 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.028 ns + Longest register pin " "Info: + Longest register to pin delay is 4.028 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns manager:inst\|small_fifo:small_fifo_Inst\|depth\[0\] 1 REG LCFF_X22_Y14_N23 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y14_N23; Fanout = 4; REG Node = 'manager:inst\|small_fifo:small_fifo_Inst\|depth\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { manager:inst|small_fifo:small_fifo_Inst|depth[0] } "NODE_NAME" } } { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 56 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.274 ns) + CELL(0.346 ns) 0.620 ns manager:inst\|small_fifo:small_fifo_Inst\|LessThan0~54 2 COMB LCCOMB_X22_Y14_N20 1 " "Info: 2: + IC(0.274 ns) + CELL(0.346 ns) = 0.620 ns; Loc. = LCCOMB_X22_Y14_N20; Fanout = 1; COMB Node = 'manager:inst\|small_fifo:small_fifo_Inst\|LessThan0~54'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.620 ns" { manager:inst|small_fifo:small_fifo_Inst|depth[0] manager:inst|small_fifo:small_fifo_Inst|LessThan0~54 } "NODE_NAME" } } { "small_fifo.v" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/small_fifo.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc.= %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(2.134 ns) 4.028 ns in_rdy 3 PIN PIN_K19 0 " "Info: 3: + IC(1.274 ns) + CELL(2.134 ns) = 4.028 ns; Loc. = PIN_K19; Fanout = 0; PIN Node = 'in_rdy'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.408 ns" { manager:inst|small_fifo:small_fifo_Inst|LessThan0~54 in_rdy } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 392 808 984 408 "in_rdy" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.480 ns ( 61.57 % ) " "Info: Total cell delay = 2.480 ns ( 61.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.548 ns ( 38.43 % ) " "Info: Total interconnect delay = 1.548 ns ( 38.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.028 ns" { manager:inst|small_fifo:small_fifo_Inst|depth[0] manager:inst|small_fifo:small_fifo_Inst|LessThan0~54 in_rdy } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.028 ns" { manager:inst|small_fifo:small_fifo_Inst|depth[0] {} manager:inst|small_fifo:small_fifo_Inst|LessThan0~54 {} in_rdy {} } { 0.000ns 0.274ns 1.274ns } { 0.000ns 0.346ns 2.134ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.482 ns" { clk clk~clkctrl manager:inst|small_fifo:small_fifo_Inst|depth[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.482 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|small_fifo:small_fifo_Inst|depth[0] {} } { 0.000ns 0.000ns 0.343ns 0.667ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.028 ns" { manager:inst|small_fifo:small_fifo_Inst|depth[0] manager:inst|small_fifo:small_fifo_Inst|LessThan0~54 in_rdy } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.028 ns" { manager:inst|small_fifo:small_fifo_Inst|depth[0] {} manager:inst|small_fifo:small_fifo_Inst|LessThan0~54 {} in_rdy {} } { 0.000ns 0.274ns 1.274ns } { 0.000ns 0.346ns 2.134ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}{ "Info" "ITDB_TH_RESULT" "manager:inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_1\|altsyncram_dni1:auto_generated\|ram_block1a0~porta_datain_reg18 in_data\[46\] clk -2.251 ns memory " "Info: th for memory \"manager:inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_1\|altsyncram_dni1:auto_generated\|ram_block1a0~porta_datain_reg18\" (data pin = \"in_data\[46\]\", clock pin = \"clk\") is -2.251 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.344 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to destination memory is 2.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 2482 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 2482; COMB Node = 'clk~clkctrl'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 504 448 616 520 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.481 ns) 2.344 ns manager:inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_1\|altsyncram_dni1:auto_generated\|ram_block1a0~porta_datain_reg18 3 MEM M4K_X32_Y16 1 " "Info: 3: + IC(0.666 ns) + CELL(0.481 ns) = 2.344 ns; Loc. = M4K_X32_Y16; Fanout = 1; MEM Node = 'manager:inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_1\|altsyncram_dni1:auto_generated\|ram_block1a0~porta_datain_reg18'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.147 ns" { clk~clkctrl manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 } "NODE_NAME" } } { "db/altsyncram_dni1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_dni1.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.335 ns ( 56.95 % ) " "Info: Total cell delay = 1.335 ns ( 56.95 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 43.05 % ) " "Info: Total interconnect delay = 1.009 ns ( 43.05 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.344 ns" { clk clk~clkctrl manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.344 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.203 ns + " "Info: + Micro hold delay of destination is 0.203 ns" { } { { "db/altsyncram_dni1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_dni1.tdf" 37 2 0 } } } 0 0 "%2!c! Micro hold delay ofdestination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.798 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 4.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns in_data\[46\] 1 PIN PIN_M2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M2; Fanout = 2; PIN Node = 'in_data\[46\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { in_data[46] } "NODE_NAME" } } { "LB.bdf" "" { Schematic "C:/Documents and Settings/Shadi/Desktop/LB/LB.bdf" { { 392 448 616 408 "in_data\[63..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.838 ns) + CELL(0.096 ns) 4.798 ns manager:inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_1\|altsyncram_dni1:auto_generated\|ram_block1a0~porta_datain_reg18 2 MEM M4K_X32_Y16 1 " "Info: 2: + IC(3.838 ns) + CELL(0.096 ns) = 4.798 ns; Loc. = M4K_X32_Y16; Fanout = 1; MEM Node = 'manager:inst\|small_fifo:small_fifo_Inst\|altsyncram:queue_rtl_1\|altsyncram_dni1:auto_generated\|ram_block1a0~porta_datain_reg18'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.934 ns" { in_data[46] manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 } "NODE_NAME" } } { "db/altsyncram_dni1.tdf" "" { Text "C:/Documents and Settings/Shadi/Desktop/LB/db/altsyncram_dni1.tdf" 37 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.960 ns ( 20.01 % ) " "Info: Total cell delay = 0.960 ns ( 20.01 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.838 ns ( 79.99 % ) " "Info: Total interconnect delay = 3.838 ns ( 79.99 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.798 ns" { in_data[46] manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.798 ns" { in_data[46] {} in_data[46]~combout {} manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 {} } { 0.000ns 0.000ns 3.838ns } { 0.000ns 0.864ns 0.096ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.344 ns" { clk clk~clkctrl manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.344 ns" { clk {} clk~combout {} clk~clkctrl {} manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.481ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.798 ns" { in_data[46] manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.798 ns" { in_data[46] {} in_data[46]~combout {} manager:inst|small_fifo:small_fifo_Inst|altsyncram:queue_rtl_1|altsyncram_dni1:auto_generated|ram_block1a0~porta_datain_reg18{} } { 0.000ns 0.000ns 3.838ns } { 0.000ns 0.864ns 0.096ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0}{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "128 " "Info: Allocated 128 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 10 18:13:08 2010 " "Info: Processing ended: Sun Jan 10 18:13:08 2010" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}