OpenCores

URL https://opencores.org/ocsvn/logicprobe/logicprobe/trunk

Subversion Repositories logicprobe

[/] [logicprobe/] [trunk/] [tst/] [sim-v/] [Makefile] - Rev 10

Go to most recent revision | Compare with Previous | Blame | View Log

#
# Makefile to build a simulation of the test circuit
#

all:            dump.vcd

show:           dump.vcd
                gtkwave dump.vcd top.cfg

dump.vcd:       top
                ./top

top:            top.v
                iverilog -Wall -o top top.v

clean:
                rm -f *~ top dump.vcd

Go to most recent revision | Compare with Previous | Blame | View Log

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.