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[/] [logicprobe/] [trunk/] [tst/] [sim-v/] [Makefile] - Rev 5

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#
# Makefile to build a simulation of the test circuit
#

all:            dump.vcd

show:           dump.vcd
                gtkwave dump.vcd top.cfg

dump.vcd:       top
                ./top

top:            top.v
                iverilog -Wall -o top top.v

clean:
                rm -f *~ top dump.vcd

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