Subversion Repositories lq057q3dc02

# Date: Thu Nov 06 22:53:43 2008
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc2vp30
SET devicefamily = virtex2p
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff896
SET removerpms = False
SET simulationfiles = Structural
SET speedgrade = -7
SET verilogsim = False
SET vhdlsim = True
SET workingdirectory = D:\MyDocuments\OpenCores\projects\lq057q3dc02\coregen\tmp