Subversion Repositories lq057q3dc02

##############################################################################
# Copyright (C) 2007 Jonathon W. Donaldson
#                    jwdonal a t opencores DOT org
#
#  This program is free software; you can redistribute it and/or modify
#  it under the terms of the GNU General Public License as published by
#  the Free Software Foundation; either version 2 of the License, or
#  (at your option) any later version.
#
#  This program is distributed in the hope that it will be useful,
#  but WITHOUT ANY WARRANTY; without even the implied warranty of
#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
#  GNU General Public License for more details.
#
#  You should have received a copy of the GNU General Public License
#  along with this program; if not, write to the Free Software
#  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
#
##############################################################################
#
# $Id: xupv2p.ucf,v 1.1 2008-11-07 00:48:12 jwdonal Exp $
#
# Description:
#   Mapping and Timing Constraints for XUPV2P Development Board.
#
# Structure:
#   - xupv2p.ucf
#   - components.vhd
#   - lq057q3dc02_tb.vhd
#   - lq057q3dc02_top.vhd
#     - dcm_sys_to_lcd.xaw
#     - video_controller.vhd
#       - enab_control.vhd
#       - hsyncx_control.vhd
#       - vsyncx_control.vhd
#       - clk_lcd_cyc_cntr.vhd
#     - image_gen_bram.vhd
#       - image_gen_bram_red.xco
#       - image_gen_bram_green.xco
#       - image_gen_bram_blue.xco
#
##############################################################################

## Resets and Clocks
NET "RSTx"         LOC = "AH1";
NET "CLK_100M_PAD" LOC = "AJ15";
NET "CLK_100M_PAD" PERIOD = 10 ns HIGH 50 %; # 100MHz System Clock

########################################

## PIN MAPPING FOR CABLE QD7597
# LCD Control Signals
NET "CLK_LCD" LOC = "P8";
NET "CLK_LCD" PERIOD = 160 ns HIGH 50 %; # 6.25MHz LCD Clock
NET "HSYNCx"  LOC = "P7";
NET "VSYNCx"  LOC = "N4";
NET "ENAB"    LOC = "AA1";
NET "RL"      LOC = "AB1";
NET "UD"      LOC = "W5";
NET "VQ"      LOC = "W6";

# Color Data Signals
NET "R<0>"  LOC = "N3";
NET "R<1>"  LOC = "P3";
NET "R<2>"  LOC = "P2";
NET "R<3>"  LOC = "R8";
NET "R<4>"  LOC = "R7";
NET "R<5>"  LOC = "P5";

NET "G<0>"  LOC = "T3";
NET "G<1>"  LOC = "T4";
NET "G<2>"  LOC = "U2";
NET "G<3>"  LOC = "U3";
NET "G<4>"  LOC = "T7";
NET "G<5>"  LOC = "T8";

NET "B<0>"  LOC = "Y2";
NET "B<1>"  LOC = "AA2";
NET "B<2>"  LOC = "V7";
NET "B<3>"  LOC = "V8";
NET "B<4>"  LOC = "W3";
NET "B<5>"  LOC = "W4";

##################################################################

### PIN MAPPING FOR LOGIC ANALYZER (same mappings as for cable QD7598 (below) but with a few uneeded outputs removed)
## Logic Analyzer external clock
#NET "CLK_25M_LA"   LOC = "L5";   # EXP_IO_10 (Logic Analyzer Clock)
#
## LCD Control Signals
#NET "CLK_LCD_LA" LOC = "T6";
#NET "HSYNCx_LA"  LOC = "T5";
#NET "VSYNCx_LA"  LOC = "V1";
#NET "ENAB_LA"    LOC = "AA4";
#
## Color Data Signals
#NET "R_LA<0>"  LOC = "U1"; # EXP_IO_36
#NET "R_LA<1>"  LOC = "R3"; # EXP_IO_35
#NET "R_LA<2>"  LOC = "R4"; # EXP_IO_34
#NET "R_LA<3>"  LOC = "R5"; # EXP_IO_33
#NET "R_LA<4>"  LOC = "R6"; # EXP_IO_32
#NET "R_LA<5>"  LOC = "T2"; # EXP_IO_31
#
## VSYNCx Controller Signals
#NET "NUM_LINES<0>" LOC = "K2"; #EXP_IO_0
#NET "NUM_LINES<1>" LOC = "L2"; #EXP_IO_1
#NET "NUM_LINES<2>" LOC = "N8"; #EXP_IO_2
#NET "NUM_LINES<3>" LOC = "N7"; #EXP_IO_3
#NET "NUM_LINES<4>" LOC = "K4"; #EXP_IO_4
#NET "NUM_LINES<5>" LOC = "K3"; #EXP_IO_5
#NET "NUM_LINES<6>" LOC = "L1"; #EXP_IO_6
#NET "NUM_LINES<7>" LOC = "M1"; #EXP_IO_7
#
#NET "HSYNCx_CNTR_STS_TOP<0>" LOC = "N6"; #EXP_IO_8
#NET "HSYNCx_CNTR_STS_TOP<1>" LOC = "N5"; #EXP_IO_9

##################################################################

### PIN MAPPING FOR CABLE QD7598
## LCD Control Signals
#NET "CLK_LCD"   LOC = "T6";
#NET "CLK_LCD" PERIOD = 160 ns HIGH 50 %; # 6.25MHz LCD Clock
#NET "HSYNCx"    LOC = "T5";
#NET "VSYNCx"    LOC = "V1";
#NET "ENAB"     LOC = "AA4";
#NET "RL"       LOC = "AA3";
#NET "UD"       LOC = "Y5";
#NET "VQ"       LOC = "Y4";
#
## Color Data Signals
#NET "R<0>"  LOC = "U1";
#NET "R<1>"  LOC = "R3";
#NET "R<2>"  LOC = "R4";
#NET "R<3>"  LOC = "R5";
#NET "R<4>"  LOC = "R6";
#NET "R<5>"  LOC = "T2";
#
#NET "G<0>"  LOC = "V6";
#NET "G<1>"  LOC = "V5";
#NET "G<2>"  LOC = "U8";
#NET "G<3>"  LOC = "U7";
#NET "G<4>"  LOC = "Y1";
#NET "G<5>"  LOC = "W1";
#
#NET "B<0>"  LOC = "AC2";
#NET "B<1>"  LOC = "AB2";
#NET "B<2>"  LOC = "AB4";
#NET "B<3>"  LOC = "AB3";
#NET "B<4>"  LOC = "W8";
#NET "B<5>"  LOC = "W7";