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[/] [lq057q3dc02/] [trunk/] [implement/] [results/] [lq057q3dc02_top.nlf] - Rev 47
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Release 9.2.04i - netgen J.40Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.Command Line: netgen -ofmt vhdl -w lq057q3dc02_top.ngcReading design 'lq057q3dc02_top.ngc' ...Flattening design ...Processing design ...Preping design's networks ...Preping design's macros ...Writing VHDL netlist 'lq057q3dc02_top.vhd' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIMsimulation primitives and has to be used with UNISIM library for correctcompilation and simulation.Number of warnings: 0Number of info messages: 1Total memory usage is 56472 kilobytes