Subversion Repositories lq057q3dc02

Release 9.2.04i par J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

NAUTILUS::  Sun Nov 09 22:14:10 2008

par -ol high -w lq057q3dc02_top.ncd lq057q3dc02_top.ncd lq057q3dc02_top.pcf 


Constraints file: lq057q3dc02_top.pcf.
Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2.
   "lq057q3dc02_top" is an NCD, version 3.1, device xc2vp30, package ff896, speed -7

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.400 Volts. (default - Range: 1.400 to 1.600 Volts)


Device speed data version:  "PRODUCTION 1.94 2007-10-19".


INFO:Par:253 - The Map -timing placement will be retained since it is likely to achieve better performance.

Device Utilization Summary:

   Number of BUFGMUXs                        2 out of 16     12%
   Number of DCMs                            1 out of 8      12%
   Number of External IOBs                  27 out of 556     4%
      Number of LOCed IOBs                  27 out of 27    100%

   Number of RAMB16s                        87 out of 136    63%
   Number of SLICEs                        127 out of 13696   1%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 9 secs 
Finished initial Timing Analysis.  REAL time: 9 secs 

Starting Router

Phase 1: 4052 unrouted;       REAL time: 20 secs 

Phase 2: 3381 unrouted;       REAL time: 21 secs 

Phase 3: 340 unrouted;       REAL time: 25 secs 

Phase 4: 340 unrouted; (0)      REAL time: 25 secs 

Phase 5: 340 unrouted; (0)      REAL time: 25 secs 

Phase 6: 340 unrouted; (0)      REAL time: 25 secs 

Phase 7: 0 unrouted; (0)      REAL time: 26 secs 

Phase 8: 0 unrouted; (0)      REAL time: 27 secs 

WARNING:Route:455 - CLK Net:CLK_LCD_OBUF may have excessive skew because 
      0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 27 secs 
Total CPU time to Router completion: 27 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        CLK_LCD_OBUF |     BUFGMUX6P| No   |  135 |  0.261     |  1.238      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.320
   The MAXIMUM PIN DELAY IS:                               8.568
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   7.164

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 9.00  d >= 9.00
   ---------   ---------   ---------   ---------   ---------   ---------
        1084         783         326          65           4           0

Timing Score: 0

Number of Timing Constraints that were not applied: 2

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  PERIOD analysis for net "DCM_LCD_CLK/CLKD | SETUP   |   150.792ns|     9.208ns|       0|           0
  V_BUF" derived from  NET "DCM_LCD_CLK/CLK | HOLD    |     0.609ns|            |       0|           0
  IN_IBUFG_OUT" PERIOD = 10 ns HIGH 50%     |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  NET "DCM_LCD_CLK/CLKIN_IBUFG_OUT" PERIOD  | N/A     |         N/A|         N/A|     N/A|         N/A
  = 10 ns HIGH 50%                          |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  NET "CLK_LCD" PERIOD = 160 ns HIGH 50%    | N/A     |         N/A|         N/A|     N/A|         N/A
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 29 secs 
Total CPU time to PAR completion: 28 secs 

Peak Memory Usage:  201 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 1

Writing design to file lq057q3dc02_top.ncd



PAR done!