Subversion Repositories lq057q3dc02

Release 9.2.04i - xst J.40
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
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TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) Partition Resource Summary
     9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "../xst.prj"

---- Target Parameters
Target Device                      : xc2vp30-ff896-7
Output File Name                   : "lq057q3dc02_top_part"

---- Source Options
Top Module Name                    : lq057q3dc02_top

---- Target Options
Equivalent register Removal        : no
Global Maximum Fanout              : 65535

---- General Options
Optimization Goal                  : SPEED
Optimization Effort                : 1
Keep Hierarchy                     : soft

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/components.vhd" in Library work_vhsic.
Package <components> compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/hsyncx_control.vhd" in Library work_vhsic.
Entity <hsyncx_control> compiled.
Entity <hsyncx_control> (Architecture <hsyncx_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/vsyncx_control.vhd" in Library work_vhsic.
Entity <vsyncx_control> compiled.
Entity <vsyncx_control> (Architecture <vsyncx_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/clk_lcd_cyc_cntr.vhd" in Library work_vhsic.
Entity <clk_lcd_cyc_cntr> compiled.
Entity <clk_lcd_cyc_cntr> (Architecture <clk_lcd_cyc_cntr_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/enab_control.vhd" in Library work_vhsic.
Entity <enab_control> compiled.
Entity <enab_control> (Architecture <enab_control_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/dcm_sys_to_lcd.vhd" in Library work_vhsic.
Entity <dcm_sys_to_lcd> compiled.
Entity <dcm_sys_to_lcd> (Architecture <BEHAVIORAL>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/video_controller.vhd" in Library work_vhsic.
Entity <video_controller> compiled.
Entity <video_controller> (Architecture <video_controller_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/image_gen_bram.vhd" in Library work_vhsic.
Entity <image_gen_bram> compiled.
Entity <image_gen_bram> (Architecture <image_gen_bram_arch>) compiled.
Compiling vhdl file "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" in Library work_vhsic.
Entity <lq057q3dc02_top> compiled.
Entity <lq057q3dc02_top> (Architecture <lq057q3dc02_top_arch>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <lq057q3dc02_top> in library <work_vhsic> (architecture <lq057q3dc02_top_arch>) with generics.
        C_BIT_DEPTH = 18
        C_BRAM_ADDR_WIDTH = 17
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_HSYNC_TH = 400
        C_HSYNC_THP = 10
        C_IMAGE_HEIGHT = 240
        C_IMAGE_WIDTH = 320
        C_LINE_NUM_WIDTH = 9
        C_NUM_CLKS_WIDTH = 9
        C_RL_STATUS = '0'
        C_UD_STATUS = '1'
        C_VQ_STATUS = '0'
        C_VSYNC_TV = 255
        C_VSYNC_TVP = 3
        C_VSYNC_TVS = 7

Analyzing hierarchy for entity <dcm_sys_to_lcd> in library <work_vhsic> (architecture <BEHAVIORAL>).

Analyzing hierarchy for entity <video_controller> in library <work_vhsic> (architecture <video_controller_arch>) with generics.
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_HSYNC_TH = 400
        C_HSYNC_THP = 10
        C_LINE_NUM_WIDTH = 9
        C_NUM_CLKS_WIDTH = 9
        C_RL_STATUS = '0'
        C_UD_STATUS = '1'
        C_VQ_STATUS = '0'
        C_VSYNC_TV = 255
        C_VSYNC_TVP = 3
        C_VSYNC_TVS = 7

Analyzing hierarchy for entity <image_gen_bram> in library <work_vhsic> (architecture <image_gen_bram_arch>) with generics.
        C_BIT_DEPTH = 18
        C_BRAM_ADDR_WIDTH = 17
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_IMAGE_HEIGHT = 240
        C_IMAGE_WIDTH = 320
        C_LINE_NUM_WIDTH = 9
        C_VSYNC_TVS = 7

Analyzing hierarchy for entity <hsyncx_control> in library <work_vhsic> (architecture <hsyncx_control_arch>) with generics.
        C_HSYNC_TH = 400
        C_HSYNC_THP = 10
        C_NUM_CLKS_WIDTH = 9

Analyzing hierarchy for entity <vsyncx_control> in library <work_vhsic> (architecture <vsyncx_control_arch>) with generics.
        C_LINE_NUM_WIDTH = 9
        C_VSYNC_TV = 255
        C_VSYNC_TVP = 3

Analyzing hierarchy for entity <clk_lcd_cyc_cntr> in library <work_vhsic> (architecture <clk_lcd_cyc_cntr_arch>) with generics.
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_LINE_NUM_WIDTH = 9
        C_VSYNC_TVS = 7

Analyzing hierarchy for entity <enab_control> in library <work_vhsic> (architecture <enab_control_arch>) with generics.
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_VSYNC_TVS = 7


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <lq057q3dc02_top> in library <work_vhsic> (Architecture <lq057q3dc02_top_arch>).
        C_BIT_DEPTH = 18
        C_BRAM_ADDR_WIDTH = 17
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_HSYNC_TH = 400
        C_HSYNC_THP = 10
        C_IMAGE_HEIGHT = 240
        C_IMAGE_WIDTH = 320
        C_LINE_NUM_WIDTH = 9
        C_NUM_CLKS_WIDTH = 9
        C_RL_STATUS = '0'
        C_UD_STATUS = '1'
        C_VQ_STATUS = '0'
        C_VSYNC_TV = 255
        C_VSYNC_TVP = 3
        C_VSYNC_TVS = 7
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKIN_IBUFG_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLK0_OUT' of component 'dcm_sys_to_lcd'.
WARNING:Xst:753 - "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd" line 307: Unconnected output port 'CLKFX_OUT' of component 'dcm_sys_to_lcd'.
Entity <lq057q3dc02_top> analyzed. Unit <lq057q3dc02_top> generated.

Analyzing Entity <dcm_sys_to_lcd> in library <work_vhsic> (Architecture <BEHAVIORAL>).
    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <CLKIN_IBUFG_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <CLKIN_IBUFG_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <CLKIN_IBUFG_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "FACTORY_JF =  C080" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLKFX_DIVIDE =  4" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  TRUE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLKDV_DIVIDE =  8.0000000000000000" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLKFX_MULTIPLY =  2" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLKIN_PERIOD =  20.0000000000000000" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "DSS_MODE =  NONE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
    Set user-defined property "STARTUP_WAIT =  TRUE" for instance <DCM_INST> in unit <dcm_sys_to_lcd>.
Entity <dcm_sys_to_lcd> analyzed. Unit <dcm_sys_to_lcd> generated.

Analyzing generic Entity <video_controller> in library <work_vhsic> (Architecture <video_controller_arch>).
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_HSYNC_TH = 400
        C_HSYNC_THP = 10
        C_LINE_NUM_WIDTH = 9
        C_NUM_CLKS_WIDTH = 9
        C_RL_STATUS = '0'
        C_UD_STATUS = '1'
        C_VQ_STATUS = '0'
        C_VSYNC_TV = 255
        C_VSYNC_TVP = 3
        C_VSYNC_TVS = 7
Entity <video_controller> analyzed. Unit <video_controller> generated.

Analyzing generic Entity <hsyncx_control> in library <work_vhsic> (Architecture <hsyncx_control_arch>).
        C_HSYNC_TH = 400
        C_HSYNC_THP = 10
        C_NUM_CLKS_WIDTH = 9
Entity <hsyncx_control> analyzed. Unit <hsyncx_control> generated.

Analyzing generic Entity <vsyncx_control> in library <work_vhsic> (Architecture <vsyncx_control_arch>).
        C_LINE_NUM_WIDTH = 9
        C_VSYNC_TV = 255
        C_VSYNC_TVP = 3
Entity <vsyncx_control> analyzed. Unit <vsyncx_control> generated.

Analyzing generic Entity <clk_lcd_cyc_cntr> in library <work_vhsic> (Architecture <clk_lcd_cyc_cntr_arch>).
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_LINE_NUM_WIDTH = 9
        C_VSYNC_TVS = 7
Entity <clk_lcd_cyc_cntr> analyzed. Unit <clk_lcd_cyc_cntr> generated.

Analyzing generic Entity <enab_control> in library <work_vhsic> (Architecture <enab_control_arch>).
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_VSYNC_TVS = 7
Entity <enab_control> analyzed. Unit <enab_control> generated.

Analyzing generic Entity <image_gen_bram> in library <work_vhsic> (Architecture <image_gen_bram_arch>).
        C_BIT_DEPTH = 18
        C_BRAM_ADDR_WIDTH = 17
        C_CLK_LCD_CYC_NUM_WIDTH = 9
        C_ENAB_TEP = 320
        C_ENAB_THE = 8
        C_IMAGE_HEIGHT = 240
        C_IMAGE_WIDTH = 320
        C_LINE_NUM_WIDTH = 9
        C_VSYNC_TVS = 7
Entity <image_gen_bram> analyzed. Unit <image_gen_bram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <hsyncx_control>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/hsyncx_control.vhd".
    Found 1-bit register for signal <HSYNCx>.
    Found 10-bit comparator less for signal <HSYNCx$cmp_lt0000> created at line 136.
    Found 9-bit up counter for signal <num_hsyncx_clks_reg>.
    Summary:
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
        inferred   1 Comparator(s).
Unit <hsyncx_control> synthesized.


Synthesizing Unit <vsyncx_control>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/vsyncx_control.vhd".
    Found finite state machine <FSM_0> for signal <Line_Cntr_cs>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | CLK_LCD (rising_edge)                          |
    | Reset              | RSTx (negative)                                |
    | Reset type         | asynchronous                                   |
    | Reset State        | ready                                          |
    | Power Up State     | frame_start                                    |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <VSYNCx>.
    Found 9-bit up counter for signal <line_num_reg>.
    Found 10-bit comparator less for signal <VSYNCx$cmp_lt0000> created at line 382.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   1 Counter(s).
        inferred   1 D-type flip-flop(s).
        inferred   1 Comparator(s).
Unit <vsyncx_control> synthesized.


Synthesizing Unit <clk_lcd_cyc_cntr>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/clk_lcd_cyc_cntr.vhd".
    Found finite state machine <FSM_1> for signal <CLK_Cntr_cs>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 12                                             |
    | Inputs             | 6                                              |
    | Outputs            | 1                                              |
    | Clock              | CLK_LCD (rising_edge)                          |
    | Reset              | RSTx (negative)                                |
    | Reset type         | asynchronous                                   |
    | Reset State        | inactive_wait_1                                |
    | Power Up State     | inactive_wait_1                                |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 10-bit comparator less for signal <CLK_Cntr_cs$cmp_lt0000> created at line 205.
    Found 9-bit up counter for signal <clk_cyc_num_reg>.
    Summary:
        inferred   1 Finite State Machine(s).
        inferred   1 Counter(s).
        inferred   1 Comparator(s).
Unit <clk_lcd_cyc_cntr> synthesized.


Synthesizing Unit <enab_control>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/enab_control.vhd".
    Found 1-bit register for signal <ENAB>.
    Found 10-bit comparator greatequal for signal <ENAB$cmp_ge0000> created at line 131.
    Found 10-bit comparator less for signal <ENAB$cmp_lt0000> created at line 131.
    Summary:
        inferred   1 D-type flip-flop(s).
        inferred   2 Comparator(s).
Unit <enab_control> synthesized.


Synthesizing Unit <dcm_sys_to_lcd>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/dcm_sys_to_lcd.vhd".
Unit <dcm_sys_to_lcd> synthesized.


Synthesizing Unit <video_controller>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/video_controller.vhd".
Unit <video_controller> synthesized.


Synthesizing Unit <image_gen_bram>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/image_gen_bram.vhd".
WARNING:Xst:646 - Signal <SINIT_wire> is assigned but never used.
    Found 17-bit up counter for signal <ADDR_wire>.
    Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0000> created at line 233.
    Found 10-bit comparator greatequal for signal <ADDR_wire$cmp_ge0001> created at line 239.
    Found 10-bit comparator less for signal <ADDR_wire$cmp_lt0000> created at line 233.
    Found 10-bit comparator less for signal <ADDR_wire$cmp_lt0001> created at line 233.
    Summary:
        inferred   1 Counter(s).
        inferred   4 Comparator(s).
Unit <image_gen_bram> synthesized.


Synthesizing Unit <lq057q3dc02_top>.
    Related source file is "D:/MyDocuments/OpenCores/projects/lq057q3dc02/design/lq057q3dc02_top.vhd".
Unit <lq057q3dc02_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                                             : 4
 17-bit up counter                                     : 1
 9-bit up counter                                      : 3
# Registers                                            : 3
 1-bit register                                        : 3
# Comparators                                          : 9
 10-bit comparator greatequal                          : 3
 10-bit comparator less                                : 6

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs> on signal <CLK_Cntr_cs[1:3]> with sequential encoding.
-------------------------------
 State             | Encoding
-------------------------------
 inactive_wait_1   | 000
 inactive_wait_2   | 010
 inactive_wait_tvs | 001
 inactive_wait_the | 011
 active            | 100
-------------------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <V_C/VSYNCx_C/Line_Cntr_cs> on signal <Line_Cntr_cs[1:2]> with gray encoding.
-------------------------
 State       | Encoding
-------------------------
 frame_start | 00
 add         | 10
 add_wait    | 11
 ready       | 01
-------------------------
Loading device for application Rf_Device from file '2vp30.nph' in environment C:\Xilinx\ISE_9_2.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 2
# Counters                                             : 4
 17-bit up counter                                     : 1
 9-bit up counter                                      : 3
# Registers                                            : 8
 Flip-Flops                                            : 8
# Comparators                                          : 9
 10-bit comparator greatequal                          : 3
 10-bit comparator less                                : 6

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <lq057q3dc02_top> ...

Optimizing unit <hsyncx_control> ...

Optimizing unit <vsyncx_control> ...

Optimizing unit <clk_lcd_cyc_cntr> ...

Optimizing unit <enab_control> ...

Optimizing unit <dcm_sys_to_lcd> ...

Optimizing unit <image_gen_bram> ...

Optimizing unit <video_controller> ...

Mapping all equations...
WARNING:Xst:2036 - Inserting OBUF on port <B<5>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<4>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<3>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<2>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<1>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <B<0>> driven by black box <image_gen_bram_blue>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<5>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<4>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<3>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<2>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<1>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <G<0>> driven by black box <image_gen_bram_green>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<5>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<4>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<3>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<2>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<1>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
WARNING:Xst:2036 - Inserting OBUF on port <R<0>> driven by black box <image_gen_bram_red>. Possible simulation mismatch.
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 52
 Flip-Flops                                            : 52

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : lq057q3dc02_top_part
Output Format                      : ngc
Optimization Goal                  : SPEED
Keep Hierarchy                     : soft

Design Statistics
# IOs                              : 27

Cell Usage :
# BELS                             : 207
#      GND                         : 6
#      INV                         : 9
#      LUT1                        : 8
#      LUT2                        : 7
#      LUT2_L                      : 5
#      LUT3                        : 25
#      LUT3_D                      : 1
#      LUT3_L                      : 1
#      LUT4                        : 52
#      LUT4_L                      : 7
#      MUXCY                       : 40
#      MUXF5                       : 1
#      VCC                         : 2
#      XORCY                       : 43
# FlipFlops/Latches                : 52
#      FDC                         : 23
#      FDCE                        : 26
#      FDP                         : 3
# Clock Buffers                    : 3
#      BUFG                        : 3
# IO Buffers                       : 27
#      IBUF                        : 1
#      IBUFG                       : 1
#      OBUF                        : 25
# DCMs                             : 1
#      DCM                         : 1
# Others                           : 3
#      image_gen_bram_blue         : 1
#      image_gen_bram_green        : 1
#      image_gen_bram_red          : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2vp30ff896-7 

 Number of Slices:                      58  out of  13696     0%  
 Number of Slice Flip Flops:            52  out of  27392     0%  
 Number of 4 input LUTs:               115  out of  27392     0%  
 Number of IOs:                         27
 Number of bonded IOBs:                 26  out of    556     4%  
 Number of GCLKs:                        3  out of     16    18%  
 Number of DCMs:                         1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK_100M_PAD                       | DCM_INST:CLKDV         | 52    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------------------------------------------------------------------+-----------------------------------------------+-------+
Control Signal                                                                                 | Buffer(FF name)                               | Load  |
-----------------------------------------------------------------------------------------------+-----------------------------------------------+-------+
V_C/HSYNCx_C/RSTx_inv(V_C/HSYNCx_C/RSTx_inv1_INV_0:O)                                          | NONE(V_C/HSYNCx_C/HSYNCx)                     | 10    |
V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv(V_C/CLK_LCD_CYCLE_Cntr/CLK_Cntr_cs_Rst_inv1_INV_0:O)| NONE(V_C/CLK_LCD_CYCLE_Cntr/clk_cyc_num_reg_1)| 12    |
IMAGE/RSTx_inv(IMAGE/RSTx_inv1_INV_0:O)                                                        | NONE(IMAGE/ADDR_wire_10)                      | 17    |
V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv(V_C/VSYNCx_C/Line_Cntr_cs_Rst_inv1_INV_0:O)                  | NONE(V_C/VSYNCx_C/line_num_reg_6)             | 12    |
V_C/ENAB_C/RSTx_inv(V_C/ENAB_C/RSTx_inv1_INV_0:O)                                              | NONE(V_C/ENAB_C/ENAB)                         | 1     |
-----------------------------------------------------------------------------------------------+-----------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -7

   Minimum period: 0.500ns (Maximum Frequency: 2000.475MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 3.390ns
   Maximum combinational path delay: 2.924ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK_100M_PAD'
  Clock period: 0.500ns (frequency: 2000.475MHz)
  Total number of paths / destination ports: 2197 / 78
-------------------------------------------------------------------------
Delay:               3.999ns (Levels of Logic = 21)
  Source:            V_C/VSYNCx_C/line_num_reg_6 (FF)
  Destination:       IMAGE/ADDR_wire_16 (FF)
  Source Clock:      CLK_100M_PAD rising 0.1X
  Destination Clock: CLK_100M_PAD rising 0.1X

  Data Path: V_C/VSYNCx_C/line_num_reg_6 to IMAGE/ADDR_wire_16
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             8   0.370   0.614  line_num_reg_6 (LINE_NUM<6>)
     end scope: 'VSYNCx_C'
     end scope: 'V_C'
     begin scope: 'IMAGE'
     LUT4:I0->O           16   0.275   0.668  Mcount_ADDR_wire_lut<0>_SW0 (N92)
     LUT4:I3->O            1   0.275   0.000  Mcount_ADDR_wire_lut<0> (N2)
     MUXCY:S->O            1   0.334   0.000  Mcount_ADDR_wire_cy<0> (Mcount_ADDR_wire_cy<0>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<1> (Mcount_ADDR_wire_cy<1>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<2> (Mcount_ADDR_wire_cy<2>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<3> (Mcount_ADDR_wire_cy<3>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<4> (Mcount_ADDR_wire_cy<4>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<5> (Mcount_ADDR_wire_cy<5>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<6> (Mcount_ADDR_wire_cy<6>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<7> (Mcount_ADDR_wire_cy<7>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<8> (Mcount_ADDR_wire_cy<8>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<9> (Mcount_ADDR_wire_cy<9>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<10> (Mcount_ADDR_wire_cy<10>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<11> (Mcount_ADDR_wire_cy<11>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<12> (Mcount_ADDR_wire_cy<12>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<13> (Mcount_ADDR_wire_cy<13>)
     MUXCY:CI->O           1   0.036   0.000  Mcount_ADDR_wire_cy<14> (Mcount_ADDR_wire_cy<14>)
     MUXCY:CI->O           0   0.036   0.000  Mcount_ADDR_wire_cy<15> (Mcount_ADDR_wire_cy<15>)
     XORCY:CI->O           1   0.708   0.000  Mcount_ADDR_wire_xor<16> (Mcount_ADDR_wire16)
     FDCE:D                    0.208          ADDR_wire_16
    ----------------------------------------
    Total                      3.999ns (2.717ns logic, 1.282ns route)
                                       (68.0% logic, 32.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK_100M_PAD'
  Total number of paths / destination ports: 54 / 54
-------------------------------------------------------------------------
Offset:              3.390ns (Levels of Logic = 2)
  Source:            V_C/HSYNCx_C/HSYNCx (FF)
  Destination:       HSYNCx (PAD)
  Source Clock:      CLK_100M_PAD rising 0.1X

  Data Path: V_C/HSYNCx_C/HSYNCx to HSYNCx
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              5   0.370   0.428  HSYNCx (HSYNCx)
     end scope: 'HSYNCx_C'
     end scope: 'V_C'
     OBUF:I->O                 2.592          HSYNCx_OBUF (HSYNCx)
    ----------------------------------------
    Total                      3.390ns (2.962ns logic, 0.428ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 18 / 18
-------------------------------------------------------------------------
Delay:               2.924ns (Levels of Logic = 2)
  Source:            IMAGE/image_BLUE_data:douta<5> (PAD)
  Destination:       B<5> (PAD)

  Data Path: IMAGE/image_BLUE_data:douta<5> to B<5>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    image_gen_bram_blue:douta<5>    1   0.000   0.000  image_BLUE_data (B<5>)
     end scope: 'IMAGE'
     OBUF:I->O                 2.592          B_5_OBUF (B<5>)
    ----------------------------------------
    Total                      2.924ns (2.924ns logic, 0.000ns route)
                                       (100.0% logic, 0.0% route)

=========================================================================
CPU : 14.75 / 15.05 s | Elapsed : 15.00 / 15.00 s
 
--> 

Total memory usage is 206148 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   22 (   0 filtered)
Number of infos    :    0 (   0 filtered)