Subversion Repositories lwrisc

|ClaiRISC_core
clk => clk_in.PADIO
rst => rst_in.PADIO
wb_din[0] => ~NO_FANOUT~
wb_din[1] => ~NO_FANOUT~
wb_din[2] => ~NO_FANOUT~
wb_din[3] => ~NO_FANOUT~
wb_din[4] => ~NO_FANOUT~
wb_din[5] => ~NO_FANOUT~
wb_din[6] => ~NO_FANOUT~
wb_din[7] => ~NO_FANOUT~
in0[0] => in0_in_0_.PADIO
in0[1] => in0_in_1_.PADIO
in0[2] => in0_in_2_.PADIO
in0[3] => in0_in_3_.PADIO
in0[4] => in0_in_4_.PADIO
in0[5] => in0_in_5_.PADIO
in0[6] => in0_in_6_.PADIO
in0[7] => in0_in_7_.PADIO
in1[0] => in1_in_0_.PADIO
in1[1] => in1_in_1_.PADIO
in1[2] => in1_in_2_.PADIO
in1[3] => in1_in_3_.PADIO
in1[4] => in1_in_4_.PADIO
in1[5] => in1_in_5_.PADIO
in1[6] => in1_in_6_.PADIO
in1[7] => in1_in_7_.PADIO
out0[0] <= out0_out_0_.PADIO
out0[1] <= out0_out_1_.PADIO
out0[2] <= out0_out_2_.PADIO
out0[3] <= out0_out_3_.PADIO
out0[4] <= out0_out_4_.PADIO
out0[5] <= out0_out_5_.PADIO
out0[6] <= out0_out_6_.PADIO
out0[7] <= out0_out_7_.PADIO
out1[0] <= out1_out_0_.PADIO
out1[1] <= out1_out_1_.PADIO
out1[2] <= out1_out_2_.PADIO
out1[3] <= out1_out_3_.PADIO
out1[4] <= out1_out_4_.PADIO
out1[5] <= out1_out_5_.PADIO
out1[6] <= out1_out_6_.PADIO
out1[7] <= out1_out_7_.PADIO


|ClaiRISC_core|wb_mem_man:mem_man
w_ins_0 => ram128x8:i_reg_file.w_ins_0
w_ins_1 => ram128x8:i_reg_file.w_ins_1
w_ins_2 => ram128x8:i_reg_file.w_ins_2
w_ins_3 => ram128x8:i_reg_file.w_ins_3
w_ins_4 => ram128x8:i_reg_file.w_ins_4
out0_0 <= out0_0__Z.REGOUT
out0_1 <= out0_1__Z.REGOUT
out0_2 <= out0_2__Z.REGOUT
out0_3 <= out0_3__Z.REGOUT
out0_4 <= out0_4__Z.REGOUT
out0_5 <= out0_5__Z.REGOUT
out0_6 <= out0_6__Z.REGOUT
out0_7 <= out0_7__Z.REGOUT
out1_0 <= out1_0__Z.REGOUT
out1_1 <= out1_1__Z.REGOUT
out1_2 <= out1_2__Z.REGOUT
out1_3 <= out1_3__Z.REGOUT
out1_4 <= out1_4__Z.REGOUT
out1_5 <= out1_5__Z.REGOUT
out1_6 <= out1_6__Z.REGOUT
out1_7 <= out1_7__Z.REGOUT
w_alu_res_1_1_0 => status_3__Z.DATAD
w_alu_res_1_1_0 => ram128x8:i_reg_file.w_alu_res_1_1_0
w_alu_res_1_3_0 => status_4__Z.DATAD
w_alu_res_1_3_0 => ram128x8:i_reg_file.w_alu_res_1_3_0
w_alu_res_1_6_0 => status_5__Z.DATAD
w_alu_res_1_6_0 => ram128x8:i_reg_file.w_alu_res_1_6_0
w_alu_res_1_6_1 => status_6__Z.DATAD
w_alu_res_1_6_1 => ram128x8:i_reg_file.w_alu_res_1_6_1
w_alu_res_1_6_2 => status_7__Z.DATAD
w_alu_res_1_6_2 => ram128x8:i_reg_file.w_alu_res_1_6_2
in0_c_0 => reg_in0_0__Z.DATAD
in0_c_1 => reg_in0_1__Z.DATAD
in0_c_2 => reg_in0_2__Z.DATAD
in0_c_3 => reg_in0_3__Z.DATAD
in0_c_4 => reg_in0_4__Z.DATAD
in0_c_5 => reg_in0_5__Z.DATAD
in0_c_6 => reg_in0_6__Z.DATAD
in0_c_7 => reg_in0_7__Z.DATAD
w_alu_res_1_0_1 => status_1__Z.DATAD
w_alu_res_1_0_1 => ram128x8:i_reg_file.w_alu_res_1_0_1
w_alu_res_1_0_2 => status_2__Z.DATAC
w_alu_res_1_0_2 => ram128x8:i_reg_file.w_alu_res_1_0_2
w_alu_res_1_0_0 <= din_r_0__Z.COMBOUT
w_alu_res_1_0_a2_1_0 => din_r_0__Z.DATAD
w_alu_res_1_0_a2_1_0 => out1_0__Z.DATAC
w_alu_res_1_0_a2_1_0 => out0_0__Z.DATAC
w_alu_res_1_0_a2_1_0 => fsr_0__Z.DATAC
w_alu_res_1_0_a2_1_1 => din_r_1__Z.DATAC
w_alu_res_1_0_a2_1_1 => out1_1__Z.DATAC
w_alu_res_1_0_a2_1_1 => out0_1__Z.DATAC
w_alu_res_1_0_a2_1_1 => fsr_1__Z.DATAC
dout_4 <= dout_4_.COMBOUT
dout_7 <= dout_7_.COMBOUT
dout_5 <= dout_5_.COMBOUT
dout_3 <= dout_3_.COMBOUT
dout_2 <= dout_2_.COMBOUT
dout_6 <= dout_6_.COMBOUT
dout_0 <= dout_0_.COMBOUT
dout_1 <= dout_1_.COMBOUT
w_alu_res_1_0_a2_2_0_0 => din_r_0__Z.DATAA
w_alu_res_1_0_a2_2_0_0 => out1_0__Z.DATAA
w_alu_res_1_0_a2_2_0_0 => out0_0__Z.DATAA
w_alu_res_1_0_a2_2_0_0 => fsr_0__Z.DATAA
w_alu_res_1_0_a2_2_0_1 => din_r_1__Z.DATAA
w_alu_res_1_0_a2_2_0_1 => out1_1__Z.DATAA
w_alu_res_1_0_a2_2_0_1 => out0_1__Z.DATAA
w_alu_res_1_0_a2_2_0_1 => fsr_1__Z.DATAA
w_alu_res_1_0_0_0 => din_r_2__Z.DATAD
w_alu_res_1_0_0_0 => out1_2__Z.DATAD
w_alu_res_1_0_0_0 => out0_2__Z.DATAD
w_alu_res_1_0_0_0 => fsr_2__Z.DATAD
w_alu_res_1_0_a2_0_0 => din_r_0__Z.DATAC
w_alu_res_1_0_a2_0_0 => out1_0__Z.DATAD
w_alu_res_1_0_a2_0_0 => out0_0__Z.DATAD
w_alu_res_1_0_a2_0_0 => fsr_0__Z.DATAD
w_alu_res_1_0_a2_0_1 => din_r_1__Z.DATAD
w_alu_res_1_0_a2_0_1 => out1_1__Z.DATAD
w_alu_res_1_0_a2_0_1 => out0_1__Z.DATAD
w_alu_res_1_0_a2_0_1 => fsr_1__Z.DATAD
w_alu_res_1_0_a2_0_2 => din_r_2__Z.DATAC
w_alu_res_1_0_a2_0_2 => out1_2__Z.DATAC
w_alu_res_1_0_a2_0_2 => out0_2__Z.DATAC
w_alu_res_1_0_a2_0_2 => fsr_2__Z.DATAC
w_alu_res_1_1_a_0 => din_r_3__Z.DATAD
w_alu_res_1_1_a_0 => out1_3__Z.DATAD
w_alu_res_1_1_a_0 => out0_3__Z.DATAD
w_alu_res_1_1_a_0 => fsr_3__Z.DATAD
w_alu_res_1_1_1_0 => din_r_3__Z.DATAC
w_alu_res_1_1_1_0 => out1_3__Z.DATAC
w_alu_res_1_1_1_0 => out0_3__Z.DATAC
w_alu_res_1_1_1_0 => fsr_3__Z.DATAC
w_alu_res_1_3_a_0 => din_r_4__Z.DATAD
w_alu_res_1_3_a_0 => out1_4__Z.DATAD
w_alu_res_1_3_a_0 => out0_4__Z.DATAD
w_alu_res_1_3_a_0 => fsr_4__Z.DATAD
w_alu_res_1_3_1_0 => din_r_4__Z.DATAC
w_alu_res_1_3_1_0 => out1_4__Z.DATAC
w_alu_res_1_3_1_0 => out0_4__Z.DATAC
w_alu_res_1_3_1_0 => fsr_4__Z.DATAC
w_alu_res_1_6_a_2 => out1_7__Z.DATAD
w_alu_res_1_6_a_2 => out0_7__Z.DATAD
w_alu_res_1_6_a_2 => fsr_7__Z.DATAD
w_alu_res_1_6_a_0 => din_r_5__Z.DATAD
w_alu_res_1_6_a_0 => out1_5__Z.DATAD
w_alu_res_1_6_a_0 => out0_5__Z.DATAD
w_alu_res_1_6_a_0 => fsr_5__Z.DATAD
w_alu_res_1_6_a_1 => din_r_6__Z.DATAD
w_alu_res_1_6_a_1 => out1_6__Z.DATAD
w_alu_res_1_6_a_1 => out0_6__Z.DATAD
w_alu_res_1_6_a_1 => fsr_6__Z.DATAD
w_alu_res_1_6_1_2 => out1_7__Z.DATAC
w_alu_res_1_6_1_2 => out0_7__Z.DATAC
w_alu_res_1_6_1_2 => fsr_7__Z.DATAC
w_alu_res_1_6_1_0 => din_r_5__Z.DATAC
w_alu_res_1_6_1_0 => out1_5__Z.DATAC
w_alu_res_1_6_1_0 => out0_5__Z.DATAC
w_alu_res_1_6_1_0 => fsr_5__Z.DATAC
w_alu_res_1_6_1_1 => din_r_6__Z.DATAC
w_alu_res_1_6_1_1 => out1_6__Z.DATAC
w_alu_res_1_6_1_1 => out0_6__Z.DATAC
w_alu_res_1_6_1_1 => fsr_6__Z.DATAC
in1_c_7 => reg_in1_7__Z.DATAC
in1_c_6 => reg_in1_6__Z.DATAC
in1_c_5 => reg_in1_5__Z.DATAC
in1_c_4 => reg_in1_4__Z.DATAC
in1_c_3 => reg_in1_3__Z.DATAC
in1_c_2 => reg_in1_2__Z.DATAC
in1_c_1 => reg_in1_1__Z.DATAC
in1_c_0 => reg_in1_0__Z.DATAC
w_ek_r_4 => wr_addr_r_3__Z.DATAD
w_ek_r_4 => wr_addr_r_4__Z.DATAD
w_ek_r_4 => dout_sn_m5_e_0_a2_a_cZ.DATAB
w_ek_r_4 => dout10_cZ.DATAA
w_ek_r_4 => dout8_cZ.DATAA
w_ek_r_4 => dout_sn_m6_0_a2_cZ.DATAA
w_ek_r_4 => write_out0_0_a3_0_o2_cZ.DATAC
w_ek_r_4 => ram128x8:i_reg_file.w_ek_r_4
w_ek_r_3 => wr_addr_r_3__Z.DATAC
w_ek_r_3 => wr_addr_r_3__Z.DATAB
w_ek_r_3 => dout_sn_m5_e_0_a2_cZ.DATAA
w_ek_r_3 => write_out0_0_a3_0_o2_cZ.DATAB
w_ek_r_3 => dout7_1_cZ.DATAA
w_ek_r_3 => dout10_2_cZ.DATAC
w_ek_r_3 => ram128x8:i_reg_file.w_ek_r_3
w_ek_r_2 => wr_addr_r_2__Z.DATAC
w_ek_r_2 => wr_addr_r_2__Z.DATAA
w_ek_r_2 => status_0_0_0_a2_1_6_.DATAB
w_ek_r_2 => status_0_0_0_a2_2_6_.DATAB
w_ek_r_2 => dout_sn_m5_e_0_a2_cZ.DATAB
w_ek_r_2 => dout7_1_cZ.DATAC
w_ek_r_2 => dout10_2_cZ.DATAD
w_ek_r_2 => ram128x8:i_reg_file.w_ek_r_2
w_ek_r_1 => wr_addr_r_1__Z.DATAC
w_ek_r_1 => wr_addr_r_1__Z.DATAA
w_ek_r_1 => dout_sn_m5_e_0_a2_a_cZ.DATAC
w_ek_r_1 => dout10_cZ.DATAB
w_ek_r_1 => dout8_cZ.DATAB
w_ek_r_1 => write_out0_0_a3_0_o2_cZ.DATAD
w_ek_r_1 => dout7_1_cZ.DATAB
w_ek_r_1 => ram128x8:i_reg_file.w_ek_r_1
w_ek_r_0 => wr_en_r_Z.DATAB
w_ek_r_0 => wr_addr_r_0__Z.DATAD
w_ek_r_0 => status_0_0_0_a2_1_6_.DATAC
w_ek_r_0 => status_0_0_0_a2_2_6_.DATAC
w_ek_r_0 => dout_sn_m5_e_0_a2_a_cZ.DATAD
w_ek_r_0 => dout10_cZ.DATAC
w_ek_r_0 => dout8_cZ.DATAC
w_ek_r_0 => dout7_1_cZ.DATAD
w_ek_r_0 => ram128x8:i_reg_file.w_ek_r_0
write_out0_0_a3_0_o2 <= write_out0_0_a3_0_o2_cZ.COMBOUT
rst_c => status_0_0_0_a2_1_6_.DATAA
rst_c => status_0_0_0_a2_2_6_.DATAA
un11_w_alu_res_carry_7 => status_6_a_0_.DATAD
w_c_2mem_i_a2_0_0 => status_6_a_0_.DATAB
N_796 => status_6_0_.DATAD
w_c_wr_r => status_6_0_.DATAB
w_z_0_a2 => status_0_i_0_a_2_.DATAD
w_z_wr_r => status_0_i_0_a_2_.DATAC
G_287 => fsr_7__Z.ENA
G_287 => fsr_6__Z.ENA
G_287 => fsr_5__Z.ENA
G_287 => fsr_4__Z.ENA
G_287 => fsr_3__Z.ENA
G_287 => fsr_2__Z.ENA
G_287 => fsr_1__Z.ENA
G_287 => fsr_0__Z.ENA
G_279 => out0_7__Z.ENA
G_279 => out0_6__Z.ENA
G_279 => out0_5__Z.ENA
G_279 => out0_4__Z.ENA
G_279 => out0_3__Z.ENA
G_279 => out0_2__Z.ENA
G_279 => out0_1__Z.ENA
G_279 => out0_0__Z.ENA
G_271 => out1_7__Z.ENA
G_271 => out1_6__Z.ENA
G_271 => out1_5__Z.ENA
G_271 => out1_4__Z.ENA
G_271 => out1_3__Z.ENA
G_271 => out1_2__Z.ENA
G_271 => out1_1__Z.ENA
G_271 => out1_0__Z.ENA
rst_i_i => rst_i_i_i.IN0
un11_w_alu_res_add7 => out1_7__Z.DATAB
un11_w_alu_res_add7 => out0_7__Z.DATAB
un11_w_alu_res_add7 => fsr_7__Z.DATAB
un11_w_alu_res_add3 => din_r_3__Z.DATAB
un11_w_alu_res_add3 => out1_3__Z.DATAB
un11_w_alu_res_add3 => out0_3__Z.DATAB
un11_w_alu_res_add3 => fsr_3__Z.DATAB
un11_w_alu_res_add4 => din_r_4__Z.DATAB
un11_w_alu_res_add4 => out1_4__Z.DATAB
un11_w_alu_res_add4 => out0_4__Z.DATAB
un11_w_alu_res_add4 => fsr_4__Z.DATAB
un11_w_alu_res_add5 => din_r_5__Z.DATAB
un11_w_alu_res_add5 => out1_5__Z.DATAB
un11_w_alu_res_add5 => out0_5__Z.DATAB
un11_w_alu_res_add5 => fsr_5__Z.DATAB
un11_w_alu_res_add6 => din_r_6__Z.DATAB
un11_w_alu_res_add6 => out1_6__Z.DATAB
un11_w_alu_res_add6 => out0_6__Z.DATAB
un11_w_alu_res_add6 => fsr_6__Z.DATAB
w_c_2mem_i_a3 => din_r_6__Z.DATAA
w_c_2mem_i_a3 => din_r_5__Z.DATAA
w_c_2mem_i_a3 => din_r_4__Z.DATAA
w_c_2mem_i_a3 => din_r_3__Z.DATAA
w_c_2mem_i_a3 => out1_7__Z.DATAA
w_c_2mem_i_a3 => out1_6__Z.DATAA
w_c_2mem_i_a3 => out1_5__Z.DATAA
w_c_2mem_i_a3 => out1_4__Z.DATAA
w_c_2mem_i_a3 => out1_3__Z.DATAA
w_c_2mem_i_a3 => out0_7__Z.DATAA
w_c_2mem_i_a3 => out0_6__Z.DATAA
w_c_2mem_i_a3 => out0_5__Z.DATAA
w_c_2mem_i_a3 => out0_4__Z.DATAA
w_c_2mem_i_a3 => out0_3__Z.DATAA
w_c_2mem_i_a3 => fsr_7__Z.DATAA
w_c_2mem_i_a3 => fsr_6__Z.DATAA
w_c_2mem_i_a3 => fsr_5__Z.DATAA
w_c_2mem_i_a3 => fsr_4__Z.DATAA
w_c_2mem_i_a3 => fsr_3__Z.DATAA
w_c_2mem_i_a3 => status_6_a_0_.DATAC
w_mem_wr_r => wr_en_r_Z.DATAC
w_mem_wr_r => write_out0_0_a3_0_o2_cZ.DATAA
w_mem_wr_r => ram128x8:i_reg_file.w_mem_wr_r
clk_c => wr_en_r_Z.CLK
clk_c => reg_in1_0__Z.CLK
clk_c => reg_in1_1__Z.CLK
clk_c => reg_in1_2__Z.CLK
clk_c => reg_in1_3__Z.CLK
clk_c => reg_in1_4__Z.CLK
clk_c => reg_in1_5__Z.CLK
clk_c => reg_in1_6__Z.CLK
clk_c => reg_in1_7__Z.CLK
clk_c => wr_addr_r_1__Z.CLK
clk_c => wr_addr_r_2__Z.CLK
clk_c => wr_addr_r_3__Z.CLK
clk_c => din_r_6__Z.CLK
clk_c => din_r_5__Z.CLK
clk_c => din_r_4__Z.CLK
clk_c => din_r_3__Z.CLK
clk_c => din_r_2__Z.CLK
clk_c => din_r_1__Z.CLK
clk_c => din_r_0__Z.CLK
clk_c => wr_addr_r_4__Z.CLK
clk_c => wr_addr_r_0__Z.CLK
clk_c => reg_in0_7__Z.CLK
clk_c => reg_in0_6__Z.CLK
clk_c => reg_in0_5__Z.CLK
clk_c => reg_in0_4__Z.CLK
clk_c => reg_in0_3__Z.CLK
clk_c => reg_in0_2__Z.CLK
clk_c => reg_in0_1__Z.CLK
clk_c => reg_in0_0__Z.CLK
clk_c => status_7__Z.CLK
clk_c => status_6__Z.CLK
clk_c => status_5__Z.CLK
clk_c => status_4__Z.CLK
clk_c => status_3__Z.CLK
clk_c => status_2__Z.CLK
clk_c => status_1__Z.CLK
clk_c => status_0__Z.CLK
clk_c => out1_7__Z.CLK
clk_c => out1_6__Z.CLK
clk_c => out1_5__Z.CLK
clk_c => out1_4__Z.CLK
clk_c => out1_3__Z.CLK
clk_c => out1_2__Z.CLK
clk_c => out1_1__Z.CLK
clk_c => out1_0__Z.CLK
clk_c => out0_7__Z.CLK
clk_c => out0_6__Z.CLK
clk_c => out0_5__Z.CLK
clk_c => out0_4__Z.CLK
clk_c => out0_3__Z.CLK
clk_c => out0_2__Z.CLK
clk_c => out0_1__Z.CLK
clk_c => out0_0__Z.CLK
clk_c => fsr_7__Z.CLK
clk_c => fsr_6__Z.CLK
clk_c => fsr_5__Z.CLK
clk_c => fsr_4__Z.CLK
clk_c => fsr_3__Z.CLK
clk_c => fsr_2__Z.CLK
clk_c => fsr_1__Z.CLK
clk_c => fsr_0__Z.CLK
clk_c => ram128x8:i_reg_file.clk_c


|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file
alt_ram_q_7 <= altsyncram_Z1:altsyncram_component_Z.q_b[7]
alt_ram_q_6 <= altsyncram_Z1:altsyncram_component_Z.q_b[6]
alt_ram_q_5 <= altsyncram_Z1:altsyncram_component_Z.q_b[5]
alt_ram_q_4 <= altsyncram_Z1:altsyncram_component_Z.q_b[4]
alt_ram_q_3 <= altsyncram_Z1:altsyncram_component_Z.q_b[3]
alt_ram_q_2 <= altsyncram_Z1:altsyncram_component_Z.q_b[2]
alt_ram_q_1 <= altsyncram_Z1:altsyncram_component_Z.q_b[1]
alt_ram_q_0 <= altsyncram_Z1:altsyncram_component_Z.q_b[0]
w_ins_4 => altsyncram_Z1:altsyncram_component_Z.address_b[4]
w_ins_3 => altsyncram_Z1:altsyncram_component_Z.address_b[3]
w_ins_2 => altsyncram_Z1:altsyncram_component_Z.address_b[2]
w_ins_1 => altsyncram_Z1:altsyncram_component_Z.address_b[1]
w_ins_0 => altsyncram_Z1:altsyncram_component_Z.address_b[0]
fsr_1 => altsyncram_Z1:altsyncram_component_Z.address_b[6]
fsr_1 => altsyncram_Z1:altsyncram_component_Z.address_a[6]
fsr_0 => altsyncram_Z1:altsyncram_component_Z.address_b[5]
fsr_0 => altsyncram_Z1:altsyncram_component_Z.address_a[5]
w_ek_r_4 => altsyncram_Z1:altsyncram_component_Z.address_a[4]
w_ek_r_3 => altsyncram_Z1:altsyncram_component_Z.address_a[3]
w_ek_r_2 => altsyncram_Z1:altsyncram_component_Z.address_a[2]
w_ek_r_1 => altsyncram_Z1:altsyncram_component_Z.address_a[1]
w_ek_r_0 => altsyncram_Z1:altsyncram_component_Z.address_a[0]
w_alu_res_1_6_2 => altsyncram_Z1:altsyncram_component_Z.data_a[7]
w_alu_res_1_6_1 => altsyncram_Z1:altsyncram_component_Z.data_a[6]
w_alu_res_1_6_0 => altsyncram_Z1:altsyncram_component_Z.data_a[5]
w_alu_res_1_3_0 => altsyncram_Z1:altsyncram_component_Z.data_a[4]
w_alu_res_1_1_0 => altsyncram_Z1:altsyncram_component_Z.data_a[3]
w_alu_res_1_0_2 => altsyncram_Z1:altsyncram_component_Z.data_a[2]
w_alu_res_1_0_1 => altsyncram_Z1:altsyncram_component_Z.data_a[1]
w_alu_res_1_0_0 => altsyncram_Z1:altsyncram_component_Z.data_a[0]
clk_c => altsyncram_Z1:altsyncram_component_Z.clock0
w_mem_wr_r => altsyncram_Z1:altsyncram_component_Z.wren_a


|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z
wren_a => altsyncram:U1.wren_a
data_a[0] => altsyncram:U1.data_a
data_a[1] => altsyncram:U1.data_a
data_a[2] => altsyncram:U1.data_a
data_a[3] => altsyncram:U1.data_a
data_a[4] => altsyncram:U1.data_a
data_a[5] => altsyncram:U1.data_a
data_a[6] => altsyncram:U1.data_a
data_a[7] => altsyncram:U1.data_a
address_a[0] => altsyncram:U1.address_a
address_a[1] => altsyncram:U1.address_a
address_a[2] => altsyncram:U1.address_a
address_a[3] => altsyncram:U1.address_a
address_a[4] => altsyncram:U1.address_a
address_a[5] => altsyncram:U1.address_a
address_a[6] => altsyncram:U1.address_a
address_b[0] => altsyncram:U1.address_b
address_b[1] => altsyncram:U1.address_b
address_b[2] => altsyncram:U1.address_b
address_b[3] => altsyncram:U1.address_b
address_b[4] => altsyncram:U1.address_b
address_b[5] => altsyncram:U1.address_b
address_b[6] => altsyncram:U1.address_b
clock0 => altsyncram:U1.clock0
q_a[0] <= altsyncram:U1.q_a
q_a[1] <= altsyncram:U1.q_a
q_a[2] <= altsyncram:U1.q_a
q_a[3] <= altsyncram:U1.q_a
q_a[4] <= altsyncram:U1.q_a
q_a[5] <= altsyncram:U1.q_a
q_a[6] <= altsyncram:U1.q_a
q_a[7] <= altsyncram:U1.q_a
q_b[0] <= altsyncram:U1.q_b
q_b[1] <= altsyncram:U1.q_b
q_b[2] <= altsyncram:U1.q_b
q_b[3] <= altsyncram:U1.q_b
q_b[4] <= altsyncram:U1.q_b
q_b[5] <= altsyncram:U1.q_b
q_b[6] <= altsyncram:U1.q_b
q_b[7] <= altsyncram:U1.q_b


|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z|altsyncram:U1
wren_a => altsyncram_hg91:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_hg91:auto_generated.data_a[0]
data_a[1] => altsyncram_hg91:auto_generated.data_a[1]
data_a[2] => altsyncram_hg91:auto_generated.data_a[2]
data_a[3] => altsyncram_hg91:auto_generated.data_a[3]
data_a[4] => altsyncram_hg91:auto_generated.data_a[4]
data_a[5] => altsyncram_hg91:auto_generated.data_a[5]
data_a[6] => altsyncram_hg91:auto_generated.data_a[6]
data_a[7] => altsyncram_hg91:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_hg91:auto_generated.address_a[0]
address_a[1] => altsyncram_hg91:auto_generated.address_a[1]
address_a[2] => altsyncram_hg91:auto_generated.address_a[2]
address_a[3] => altsyncram_hg91:auto_generated.address_a[3]
address_a[4] => altsyncram_hg91:auto_generated.address_a[4]
address_a[5] => altsyncram_hg91:auto_generated.address_a[5]
address_a[6] => altsyncram_hg91:auto_generated.address_a[6]
address_b[0] => altsyncram_hg91:auto_generated.address_b[0]
address_b[1] => altsyncram_hg91:auto_generated.address_b[1]
address_b[2] => altsyncram_hg91:auto_generated.address_b[2]
address_b[3] => altsyncram_hg91:auto_generated.address_b[3]
address_b[4] => altsyncram_hg91:auto_generated.address_b[4]
address_b[5] => altsyncram_hg91:auto_generated.address_b[5]
address_b[6] => altsyncram_hg91:auto_generated.address_b[6]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_hg91:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_hg91:auto_generated.q_a[0]
q_a[1] <= altsyncram_hg91:auto_generated.q_a[1]
q_a[2] <= altsyncram_hg91:auto_generated.q_a[2]
q_a[3] <= altsyncram_hg91:auto_generated.q_a[3]
q_a[4] <= altsyncram_hg91:auto_generated.q_a[4]
q_a[5] <= altsyncram_hg91:auto_generated.q_a[5]
q_a[6] <= altsyncram_hg91:auto_generated.q_a[6]
q_a[7] <= altsyncram_hg91:auto_generated.q_a[7]
q_b[0] <= altsyncram_hg91:auto_generated.q_b[0]
q_b[1] <= altsyncram_hg91:auto_generated.q_b[1]
q_b[2] <= altsyncram_hg91:auto_generated.q_b[2]
q_b[3] <= altsyncram_hg91:auto_generated.q_b[3]
q_b[4] <= altsyncram_hg91:auto_generated.q_b[4]
q_b[5] <= altsyncram_hg91:auto_generated.q_b[5]
q_b[6] <= altsyncram_hg91:auto_generated.q_b[6]
q_b[7] <= altsyncram_hg91:auto_generated.q_b[7]


|ClaiRISC_core|wb_mem_man:mem_man|ram128x8:i_reg_file|altsyncram_Z1:altsyncram_component_Z|altsyncram:U1|altsyncram_hg91:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
address_b[5] => ram_block1a0.PORTBADDR5
address_b[5] => ram_block1a1.PORTBADDR5
address_b[5] => ram_block1a2.PORTBADDR5
address_b[5] => ram_block1a3.PORTBADDR5
address_b[5] => ram_block1a4.PORTBADDR5
address_b[5] => ram_block1a5.PORTBADDR5
address_b[5] => ram_block1a6.PORTBADDR5
address_b[5] => ram_block1a7.PORTBADDR5
address_b[6] => ram_block1a0.PORTBADDR6
address_b[6] => ram_block1a1.PORTBADDR6
address_b[6] => ram_block1a2.PORTBADDR6
address_b[6] => ram_block1a3.PORTBADDR6
address_b[6] => ram_block1a4.PORTBADDR6
address_b[6] => ram_block1a5.PORTBADDR6
address_b[6] => ram_block1a6.PORTBADDR6
address_b[6] => ram_block1a7.PORTBADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_a[0] <= <UNC>
q_a[1] <= <UNC>
q_a[2] <= <UNC>
q_a[3] <= <UNC>
q_a[4] <= <UNC>
q_a[5] <= <UNC>
q_a[6] <= <UNC>
q_a[7] <= <UNC>
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE


|ClaiRISC_core|pram:program_rom
sclrsclrw_pc_nxt_0_0_a2_x_0 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_0
sclrsclrw_pc_nxt_0_0_a2_x_1 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_1
sclrsclrw_pc_nxt_0_0_a2_x_2 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_2
sclrsclrw_pc_nxt_0_0_a2_x_3 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_3
sclrsclrw_pc_nxt_0_0_a2_x_4 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_4
sclrsclrw_pc_nxt_0_0_a2_x_5 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_5
sclrsclrw_pc_nxt_0_0_a2_x_6 => rom128x12:i_alt_ram.sclrsclrw_pc_nxt_0_0_a2_x_6
w_ins_0 <= rom128x12:i_alt_ram.w_ins_0
w_ins_1 <= rom128x12:i_alt_ram.w_ins_1
w_ins_2 <= rom128x12:i_alt_ram.w_ins_2
w_ins_3 <= rom128x12:i_alt_ram.w_ins_3
w_ins_4 <= rom128x12:i_alt_ram.w_ins_4
w_ins_6 <= rom128x12:i_alt_ram.w_ins_6
w_ins_7 <= rom128x12:i_alt_ram.w_ins_7
clk_c => rom128x12:i_alt_ram.clk_c
w_mem_wr <= rom128x12:i_alt_ram.w_mem_wr


|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram
w_ins_7 <= altsyncram_Z2:altsyncram_component_Z.q_a[7]
w_ins_6 <= altsyncram_Z2:altsyncram_component_Z.q_a[6]
w_ins_4 <= altsyncram_Z2:altsyncram_component_Z.q_a[4]
w_ins_3 <= altsyncram_Z2:altsyncram_component_Z.q_a[3]
w_ins_2 <= altsyncram_Z2:altsyncram_component_Z.q_a[2]
w_ins_1 <= altsyncram_Z2:altsyncram_component_Z.q_a[1]
w_ins_0 <= altsyncram_Z2:altsyncram_component_Z.q_a[0]
sclrsclrw_pc_nxt_0_0_a2_x_6 => altsyncram_Z2:altsyncram_component_Z.address_a[6]
sclrsclrw_pc_nxt_0_0_a2_x_5 => altsyncram_Z2:altsyncram_component_Z.address_a[5]
sclrsclrw_pc_nxt_0_0_a2_x_4 => altsyncram_Z2:altsyncram_component_Z.address_a[4]
sclrsclrw_pc_nxt_0_0_a2_x_3 => altsyncram_Z2:altsyncram_component_Z.address_a[3]
sclrsclrw_pc_nxt_0_0_a2_x_2 => altsyncram_Z2:altsyncram_component_Z.address_a[2]
sclrsclrw_pc_nxt_0_0_a2_x_1 => altsyncram_Z2:altsyncram_component_Z.address_a[1]
sclrsclrw_pc_nxt_0_0_a2_x_0 => altsyncram_Z2:altsyncram_component_Z.address_a[0]
w_mem_wr <= altsyncram_Z2:altsyncram_component_Z.q_a[5]
clk_c => altsyncram_Z2:altsyncram_component_Z.clock0


|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z
address_a[0] => altsyncram:U1.address_a
address_a[1] => altsyncram:U1.address_a
address_a[2] => altsyncram:U1.address_a
address_a[3] => altsyncram:U1.address_a
address_a[4] => altsyncram:U1.address_a
address_a[5] => altsyncram:U1.address_a
address_a[6] => altsyncram:U1.address_a
clock0 => altsyncram:U1.clock0
q_a[0] <= altsyncram:U1.q_a
q_a[1] <= altsyncram:U1.q_a
q_a[2] <= altsyncram:U1.q_a
q_a[3] <= altsyncram:U1.q_a
q_a[4] <= altsyncram:U1.q_a
q_a[5] <= altsyncram:U1.q_a
q_a[6] <= altsyncram:U1.q_a
q_a[7] <= altsyncram:U1.q_a
q_b[0] <= altsyncram:U1.q_b


|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z|altsyncram:U1
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_u8r:auto_generated.address_a[0]
address_a[1] => altsyncram_u8r:auto_generated.address_a[1]
address_a[2] => altsyncram_u8r:auto_generated.address_a[2]
address_a[3] => altsyncram_u8r:auto_generated.address_a[3]
address_a[4] => altsyncram_u8r:auto_generated.address_a[4]
address_a[5] => altsyncram_u8r:auto_generated.address_a[5]
address_a[6] => altsyncram_u8r:auto_generated.address_a[6]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_u8r:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_u8r:auto_generated.q_a[0]
q_a[1] <= altsyncram_u8r:auto_generated.q_a[1]
q_a[2] <= altsyncram_u8r:auto_generated.q_a[2]
q_a[3] <= altsyncram_u8r:auto_generated.q_a[3]
q_a[4] <= altsyncram_u8r:auto_generated.q_a[4]
q_a[5] <= altsyncram_u8r:auto_generated.q_a[5]
q_a[6] <= altsyncram_u8r:auto_generated.q_a[6]
q_a[7] <= altsyncram_u8r:auto_generated.q_a[7]
q_b[0] <= altsyncram_u8r:auto_generated.q_b[0]


|ClaiRISC_core|pram:program_rom|rom128x12:i_alt_ram|altsyncram_Z2:altsyncram_component_Z|altsyncram:U1|altsyncram_u8r:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_b[0] <= <UNC>