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[/] [lwrisc/] [trunk/] [QU2/] [db/] [ClaiRISC_core.hif] - Rev 19

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Version 4.2 Build 157 12/07/2004 SJ Full Version
32
1575
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
RETIME_OFF
REMAP_OFF
0
-- Start Partition --
|
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP
Off
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
Off
STATE_MACHINE_PROCESSING
Auto
STRATIXII_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONE_OPTIMIZATION_TECHNIQUE
Balanced
CYCLONEII_OPTIMIZATION_TECHNIQUE
Balanced
STRATIX_OPTIMIZATION_TECHNIQUE
Balanced
MAXII_OPTIMIZATION_TECHNIQUE
Balanced
----
-- End Partition --
# entity
ClaiRISC_core
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(0).cnf
db|ClaiRISC_core.(0).cnf
# end
# entity
wb_mem_man
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(1).cnf
db|ClaiRISC_core.(1).cnf
# end
# entity
ram128x8
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(2).cnf
db|ClaiRISC_core.(2).cnf
# end
# entity
altsyncram_Z1
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(3).cnf
db|ClaiRISC_core.(3).cnf
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus42|libraries|megafunctions|altsyncram.tdf
1101745298
6
# storage
db|ClaiRISC_core.(4).cnf
db|ClaiRISC_core.(4).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
7
PARAMETER_UNKNOWN
USR
NUMWORDS_A
128
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_UNKNOWN
USR
WIDTHAD_B
7
PARAMETER_UNKNOWN
USR
NUMWORDS_B
128
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_hg91
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
address_b
address_b
clock0
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
}
# include_file {
c:|altera|quartus42|libraries|megafunctions|stratix_ram_block.inc
1094871114
c:|altera|quartus42|libraries|megafunctions|lpm_mux.inc
1094870318
c:|altera|quartus42|libraries|megafunctions|lpm_decode.inc
1094870100
c:|altera|quartus42|libraries|megafunctions|aglobal42.inc
1101745276
c:|altera|quartus42|libraries|megafunctions|altsyncram.inc
1094868954
c:|altera|quartus42|libraries|megafunctions|a_rdenreg.inc
1094867530
c:|altera|quartus42|libraries|megafunctions|altrom.inc
1094868876
c:|altera|quartus42|libraries|megafunctions|altram.inc
1094868838
c:|altera|quartus42|libraries|megafunctions|altdpram.inc
1094868494
c:|altera|quartus42|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_hg91
# case_insensitive
# source_file
db|altsyncram_hg91.tdf
1205137604
6
# storage
db|ClaiRISC_core.(5).cnf
db|ClaiRISC_core.(5).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
none
0
}
# end
# entity
pram
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(6).cnf
db|ClaiRISC_core.(6).cnf
# end
# entity
rom128x12
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(7).cnf
db|ClaiRISC_core.(7).cnf
# end
# entity
altsyncram_Z2
# case_sensitive
# source_file
..|SYN|rev_1|ClaiRISC_core.vqm
1205137544
25
# storage
db|ClaiRISC_core.(8).cnf
db|ClaiRISC_core.(8).cnf
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus42|libraries|megafunctions|altsyncram.tdf
1101745298
6
# storage
db|ClaiRISC_core.(9).cnf
db|ClaiRISC_core.(9).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
7
PARAMETER_UNKNOWN
USR
NUMWORDS_A
128
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
init_file.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_u8r
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_a
address_a
clock0
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
}
# include_file {
c:|altera|quartus42|libraries|megafunctions|stratix_ram_block.inc
1094871114
c:|altera|quartus42|libraries|megafunctions|lpm_mux.inc
1094870318
c:|altera|quartus42|libraries|megafunctions|lpm_decode.inc
1094870100
c:|altera|quartus42|libraries|megafunctions|aglobal42.inc
1101745276
c:|altera|quartus42|libraries|megafunctions|altsyncram.inc
1094868954
c:|altera|quartus42|libraries|megafunctions|a_rdenreg.inc
1094867530
c:|altera|quartus42|libraries|megafunctions|altrom.inc
1094868876
c:|altera|quartus42|libraries|megafunctions|altram.inc
1094868838
c:|altera|quartus42|libraries|megafunctions|altdpram.inc
1094868494
c:|altera|quartus42|libraries|megafunctions|altqpram.inc
1094868820
}
# end
# entity
altsyncram_u8r
# case_insensitive
# source_file
db|altsyncram_u8r.tdf
1205137606
6
# storage
db|ClaiRISC_core.(10).cnf
db|ClaiRISC_core.(10).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
clock0
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_b0
}
# memory_file {
init_file.mif
0
}
# end
# complete

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