Subversion Repositories lwrisc

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 10 16:26:40 2008 " "Info: Processing started: Mon Mar 10 16:26:40 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off ClaiRISC -c ClaiRISC_core " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ClaiRISC -c ClaiRISC_core" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../SYN/rev_1/ClaiRISC_core.vqm 7 7 " "Info: Found 7 design units, including 7 entities, in source file ../SYN/rev_1/ClaiRISC_core.vqm" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_Z1 " "Info: Found entity 1: altsyncram_Z1" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 30 21 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 ram128x8 " "Info: Found entity 2: ram128x8" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 75 16 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 wb_mem_man " "Info: Found entity 3: wb_mem_man" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 206 18 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 altsyncram_Z2 " "Info: Found entity 4: altsyncram_Z2" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2731 21 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 rom128x12 " "Info: Found entity 5: rom128x12" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2761 17 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 pram " "Info: Found entity 6: pram" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2851 12 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 ClaiRISC_core " "Info: Found entity 7: ClaiRISC_core" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2927 21 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus42/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hg91.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hg91.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hg91 " "Info: Found entity 1: altsyncram_hg91" {  } { { "db/altsyncram_hg91.tdf" "" { Text "D:/LWRISC/QU2/db/altsyncram_hg91.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_u8r.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_u8r.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_u8r " "Info: Found entity 1: altsyncram_u8r" {  } { { "db/altsyncram_u8r.tdf" "" { Text "D:/LWRISC/QU2/db/altsyncram_u8r.tdf" 40 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCDB_CDB_FILE_NOT_FOUND" "D:/LWRISC/QU2/init_file.mif " "Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File D:/LWRISC/QU2/init_file.mif -- setting all initial values to 0" {  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "8 " "Warning: Design contains 8 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[0\] " "Warning: No output dependent on input pin \"wb_din\[0\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[1\] " "Warning: No output dependent on input pin \"wb_din\[1\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[2\] " "Warning: No output dependent on input pin \"wb_din\[2\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[3\] " "Warning: No output dependent on input pin \"wb_din\[3\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[4\] " "Warning: No output dependent on input pin \"wb_din\[4\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[5\] " "Warning: No output dependent on input pin \"wb_din\[5\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[6\] " "Warning: No output dependent on input pin \"wb_din\[6\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "wb_din\[7\] " "Warning: No output dependent on input pin \"wb_din\[7\]\"" {  } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2938 21 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "305 " "Info: Implemented 305 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "26 " "Info: Implemented 26 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "247 " "Info: Implemented 247 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 10 16:26:47 2008 " "Info: Processing ended: Mon Mar 10 16:26:47 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}