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https://opencores.org/ocsvn/lwrisc/lwrisc/trunk
Subversion Repositories lwrisc
[/] [lwrisc/] [trunk/] [QU2/] [db/] [ClaiRISC_core.tan.qmsg] - Rev 19
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 10 16:27:22 2008 " "Info: Processing started: Mon Mar 10 16:27:22 2008" { } { } 0} } { } 4}{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off ClaiRISC -c ClaiRISC_core --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off ClaiRISC -c ClaiRISC_core --timing_analysis_only" { } { } 0}{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2936 12 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register w_ek_r\[3\] register wb_mem_man:mem_man\|status\[2\] 66.21 MHz 15.103 ns Internal " "Info: Clock \"clk\" has Internal fmax of 66.21 MHz between source register \"w_ek_r\[3\]\" and destination register \"wb_mem_man:mem_man\|status\[2\]\" (period= 15.103 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.878 ns + Longest register register " "Info: + Longest register to register delay is 14.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns w_ek_r\[3\] 1 REG LC_X15_Y13_N2 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y13_N2; Fanout = 8; REG Node = 'w_ek_r\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { w_ek_r[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2950 19 0 } } }0} { "Info" "ITDB_NODE_DELAY" "IC(2.112 ns) + CELL(0.454 ns) 2.566 ns wb_mem_man:mem_man\|dout7_1 2 COMB LC_X15_Y13_N5 5 " "Info: 2: + IC(2.112 ns) + CELL(0.454 ns) = 2.566 ns; Loc. = LC_X15_Y13_N5; Fanout = 5; COMB Node = 'wb_mem_man:mem_man\|dout7_1'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.566 ns" { w_ek_r[3] wb_mem_man:mem_man|dout7_1 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 522 15 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.226 ns) + CELL(0.454 ns) 4.246 ns wb_mem_man:mem_man\|dout_3_a\[3\] 3 COMB LC_X13_Y11_N4 1 " "Info: 3: + IC(1.226 ns) + CELL(0.454 ns) = 4.246 ns; Loc. = LC_X13_Y11_N4; Fanout = 1; COMB Node = 'wb_mem_man:mem_man\|dout_3_a\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.680 ns" { wb_mem_man:mem_man|dout7_1 wb_mem_man:mem_man|dout_3_a[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 510 21 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.951 ns) + CELL(0.225 ns) 5.422 ns wb_mem_man:mem_man\|dout_3_Z\[3\] 4 COMB LC_X14_Y13_N6 1 " "Info: 4: + IC(0.951 ns) + CELL(0.225 ns) = 5.422 ns; Loc. = LC_X14_Y13_N6; Fanout = 1; COMB Node = 'wb_mem_man:mem_man\|dout_3_Z\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.176 ns" { wb_mem_man:mem_man|dout_3_a[3] wb_mem_man:mem_man|dout_3_Z[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 509 21 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns)+ CELL(0.088 ns) 5.650 ns wb_mem_man:mem_man\|dout_a\[3\] 5 COMB LC_X14_Y13_N7 1 " "Info: 5: + IC(0.140 ns) + CELL(0.088 ns) = 5.650 ns; Loc. = LC_X14_Y13_N7; Fanout = 1; COMB Node = 'wb_mem_man:mem_man\|dout_a\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.228 ns" { wb_mem_man:mem_man|dout_3_Z[3] wb_mem_man:mem_man|dout_a[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 508 19 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.454 ns) 6.441 ns wb_mem_man:mem_man\|dout_3 6 COMB LC_X14_Y13_N5 20 " "Info: 6: + IC(0.337 ns) + CELL(0.454 ns) = 6.441 ns; Loc. = LC_X14_Y13_N5; Fanout = 20; COMB Node = 'wb_mem_man:mem_man\|dout_3'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.791 ns" { wb_mem_man:mem_man|dout_a[3] wb_mem_man:mem_man|dout_3 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 346 16 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.529 ns) + CELL(0.333 ns) 8.303 ns un74_w_alu_res_cout\[3\]~COUT1 7 COMB LC_X14_Y11_N7 2 " "Info: 7: + IC(1.529 ns) + CELL(0.333 ns) = 8.303 ns; Loc. = LC_X14_Y11_N7; Fanout = 2; COMB Node = 'un74_w_alu_res_cout\[3\]~COUT1'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.862 ns" { wb_mem_man:mem_man|dout_3 un74_w_alu_res_cout[3]~COUT1 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2991 32 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.468 ns) 8.771 ns un74_w_alu_res\[5\] 8 COMB LC_X14_Y11_N8 1 " "Info: 8: + IC(0.000 ns) + CELL(0.468 ns) = 8.771 ns; Loc. = LC_X14_Y11_N8; Fanout = 1; COMB Node = 'un74_w_alu_res\[5\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.468 ns" { un74_w_alu_res_cout[3]~COUT1 un74_w_alu_res[5] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2979 27 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.337 ns) + CELL(0.225 ns) 9.333 ns w_alu_res_1_6_1_a\[5\] 9 COMB LC_X14_Y11_N1 1 " "Info: 9: + IC(0.337 ns) + CELL(0.225 ns) = 9.333 ns; Loc. = LC_X14_Y11_N1; Fanout = 1; COMB Node = 'w_alu_res_1_6_1_a\[5\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.562ns" { un74_w_alu_res[5] w_alu_res_1_6_1_a[5] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2981 30 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 9.561 ns w_alu_res_1_6_1\[5\] 10 COMB LC_X14_Y11_N2 6 " "Info: 10: + IC(0.140 ns) + CELL(0.088 ns) = 9.561 ns; Loc. = LC_X14_Y11_N2; Fanout = 6; COMB Node = 'w_alu_res_1_6_1\[5\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.228 ns" { w_alu_res_1_6_1_a[5] w_alu_res_1_6_1[5] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2953 28 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.340 ns) 10.887 ns w_alu_res_1_6\[5\] 11 COMB LC_X13_Y13_N0 3 " "Info: 11: + IC(0.986 ns) + CELL(0.340 ns) = 10.887 ns; Loc. = LC_X13_Y13_N0; Fanout = 3; COMB Node ='w_alu_res_1_6\[5\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.326 ns" { w_alu_res_1_6_1[5] w_alu_res_1_6[5] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2967 26 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.088 ns) 12.875 ns w_z_0_a2_a 12 COMB LC_X12_Y11_N8 1 " "Info: 12: + IC(1.900 ns) + CELL(0.088 ns) = 12.875 ns; Loc. = LC_X12_Y11_N8; Fanout = 1; COMB Node = 'w_z_0_a2_a'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.988 ns" { w_alu_res_1_6[5] w_z_0_a2_a } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 3025 18 0 } } } 0} {"Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.340 ns) 13.529 ns w_z_0_a2 13 COMB LC_X12_Y11_N7 1 " "Info: 13: + IC(0.314 ns) + CELL(0.340 ns) = 13.529 ns; Loc. = LC_X12_Y11_N7; Fanout = 1; COMB Node = 'w_z_0_a2'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.654 ns" { w_z_0_a2_a w_z_0_a2 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 3024 16 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.454 ns) 14.322 ns wb_mem_man:mem_man\|status_0_i_0_a\[2\] 14 COMB LC_X12_Y11_N1 1 " "Info: 14: + IC(0.339 ns) + CELL(0.454 ns) = 14.322 ns; Loc. = LC_X12_Y11_N1; Fanout = 1; COMB Node = 'wb_mem_man:mem_man\|status_0_i_0_a\[2\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.793 ns" { w_z_0_a2 wb_mem_man:mem_man|status_0_i_0_a[2] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 503 27 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.238 ns) 14.878 ns wb_mem_man:mem_man\|status\[2\] 15 REG LC_X12_Y11_N0 2 " "Info: 15: + IC(0.318 ns) + CELL(0.238 ns) = 14.878 ns; Loc. = LC_X12_Y11_N0; Fanout = 2; REG Node = 'wb_mem_man:mem_man\|status\[2\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "0.556 ns" { wb_mem_man:mem_man|status_0_i_0_a[2] wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 500 19 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.249 ns 28.56 % " "Info: Total cell delay = 4.249 ns (28.56 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.629 ns 71.44 % " "Info: Total interconnect delay = 10.629 ns ( 71.44 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "14.878 ns" { w_ek_r[3] wb_mem_man:mem_man|dout7_1 wb_mem_man:mem_man|dout_3_a[3] wb_mem_man:mem_man|dout_3_Z[3] wb_mem_man:mem_man|dout_a[3] wb_mem_man:mem_man|dout_3 un74_w_alu_res_cout[3]~COUT1 un74_w_alu_res[5] w_alu_res_1_6_1_a[5] w_alu_res_1_6_1[5] w_alu_res_1_6[5] w_z_0_a2_a w_z_0_a2 wb_mem_man:mem_man|status_0_i_0_a[2] wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "14.878 ns" { w_ek_r[3] wb_mem_man:mem_man|dout7_1 wb_mem_man:mem_man|dout_3_a[3] wb_mem_man:mem_man|dout_3_Z[3] wb_mem_man:mem_man|dout_a[3] wb_mem_man:mem_man|dout_3 un74_w_alu_res_cout[3]~COUT1 un74_w_alu_res[5] w_alu_res_1_6_1_a[5] w_alu_res_1_6_1[5] w_alu_res_1_6[5] w_z_0_a2_a w_z_0_a2 wb_mem_man:mem_man|status_0_i_0_a[2] wb_mem_man:mem_man|status[2] } { 0.000ns 2.112ns 1.226ns 0.951ns 0.140ns 0.337ns 1.529ns 0.000ns 0.337ns 0.140ns 0.986ns 1.900ns 0.314ns 0.339ns 0.318ns } { 0.000ns 0.454ns 0.454ns 0.225ns 0.088ns 0.454ns 0.333ns 0.468ns 0.225ns 0.088ns 0.340ns 0.088ns 0.340ns 0.454ns 0.238ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.023 ns - Smallest " "Info: - Smallest clock skew is -0.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.248 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.248 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 126 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 126; CLK Node = 'clk'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { clk } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2936 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.547 ns) 2.248 ns wb_mem_man:mem_man\|status\[2\] 2 REG LC_X12_Y11_N0 2 " "Info: 2: + IC(0.571 ns) + CELL(0.547 ns) = 2.248 ns; Loc. = LC_X12_Y11_N0; Fanout = 2; REG Node = 'wb_mem_man:mem_man\|status\[2\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.118 ns" { clk wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 500 19 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 74.60 % " "Info: Total cell delay = 1.677 ns ( 74.60 % )" { } {} 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.571 ns 25.40 % " "Info: Total interconnect delay = 0.571 ns ( 25.40 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.248 ns" { clk wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.248 ns" { clk clk~out0 wb_mem_man:mem_man|status[2] } { 0.000ns 0.000ns 0.571ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.271 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 126 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 126; CLK Node = 'clk'" { } { {"D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { clk } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2936 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns w_ek_r\[3\] 2 REG LC_X15_Y13_N2 8 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X15_Y13_N2; Fanout = 8; REG Node = 'w_ek_r\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.141 ns" { clk w_ek_r[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2950 19 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 73.84 % " "Info: Total cell delay = 1.677 ns ( 73.84 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 26.16 % " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clk w_ek_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 w_ek_r[3] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.248 ns" { clk wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.248 ns" { clk clk~out0 wb_mem_man:mem_man|status[2] } { 0.000ns 0.000ns 0.571ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clk w_ek_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 w_ek_r[3] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2950 19 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 500 19 0 } } } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "14.878 ns" { w_ek_r[3] wb_mem_man:mem_man|dout7_1 wb_mem_man:mem_man|dout_3_a[3] wb_mem_man:mem_man|dout_3_Z[3] wb_mem_man:mem_man|dout_a[3] wb_mem_man:mem_man|dout_3 un74_w_alu_res_cout[3]~COUT1 un74_w_alu_res[5] w_alu_res_1_6_1_a[5] w_alu_res_1_6_1[5] w_alu_res_1_6[5] w_z_0_a2_a w_z_0_a2 wb_mem_man:mem_man|status_0_i_0_a[2] wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "14.878 ns" { w_ek_r[3] wb_mem_man:mem_man|dout7_1 wb_mem_man:mem_man|dout_3_a[3] wb_mem_man:mem_man|dout_3_Z[3] wb_mem_man:mem_man|dout_a[3] wb_mem_man:mem_man|dout_3 un74_w_alu_res_cout[3]~COUT1 un74_w_alu_res[5] w_alu_res_1_6_1_a[5] w_alu_res_1_6_1[5] w_alu_res_1_6[5] w_z_0_a2_a w_z_0_a2 wb_mem_man:mem_man|status_0_i_0_a[2] wb_mem_man:mem_man|status[2] } { 0.000ns 2.112ns 1.226ns 0.951ns 0.140ns 0.337ns 1.529ns 0.000ns 0.337ns 0.140ns 0.986ns 1.900ns 0.314ns 0.339ns 0.318ns } { 0.000ns 0.454ns 0.454ns 0.225ns 0.088ns 0.454ns 0.333ns 0.468ns 0.225ns 0.088ns 0.340ns 0.088ns 0.340ns 0.454ns 0.238ns } } } { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.248 ns" { clk wb_mem_man:mem_man|status[2] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.248 ns" { clk clk~out0 wb_mem_man:mem_man|status[2] } { 0.000ns 0.000ns 0.571ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clk w_ek_r[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 w_ek_r[3] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } } 0}{ "Info" "ITDB_TSU_RESULT" "wb_mem_man:mem_man\|out1_6 rst clk 6.893 ns register " "Info: tsu for register \"wb_mem_man:mem_man\|out1_6\" (data pin = \"rst\", clock pin = \"clk\") is 6.893 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.135 ns + Longest pin register " "Info: + Longest pin to register delay is 9.135 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.135 ns) 1.135 ns rst 1 PIN PIN_215 43 " "Info: 1: + IC(0.000 ns) + CELL(1.135 ns) = 1.135 ns; Loc. = PIN_215; Fanout = 43; PIN Node = 'rst'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { rst } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2937 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.169 ns) + CELL(0.340 ns) 6.644 ns G_271 2 COMB LC_X13_Y9_N0 8 " "Info: 2: + IC(5.169 ns) + CELL(0.340 ns) = 6.644 ns; Loc. =LC_X13_Y9_N0; Fanout = 8; COMB Node = 'G_271'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "5.509 ns" { rst G_271 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 3020 13 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.824 ns) + CELL(0.667 ns) 9.135 ns wb_mem_man:mem_man\|out1_6 3 REG LC_X12_Y14_N2 1 " "Info: 3: + IC(1.824 ns) + CELL(0.667 ns) = 9.135 ns; Loc. = LC_X12_Y14_N2; Fanout = 1; REG Node = 'wb_mem_man:mem_man\|out1_6'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.491 ns" { G_271 wb_mem_man:mem_man|out1_6 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 323 16 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.142 ns 23.45 % " "Info: Total cell delay = 2.142 ns ( 23.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.993 ns 76.55 % " "Info: Total interconnect delay = 6.993 ns ( 76.55 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "9.135 ns" { rst G_271 wb_mem_man:mem_man|out1_6 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.135 ns" { rst rst~out0 G_271 wb_mem_man:mem_man|out1_6 } { 0.000ns 0.000ns 5.169ns 1.824ns } { 0.000ns 1.135ns 0.340ns 0.667ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 323 16 0 } }} 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.271 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 126 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 126; CLK Node = 'clk'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { clk } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2936 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns wb_mem_man:mem_man\|out1_6 2 REG LC_X12_Y14_N2 1 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X12_Y14_N2; Fanout = 1; REG Node = 'wb_mem_man:mem_man\|out1_6'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.141 ns" { clk wb_mem_man:mem_man|out1_6 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 323 16 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 73.84 % " "Info: Total cell delay = 1.677 ns ( 73.84 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 26.16 % " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clk wb_mem_man:mem_man|out1_6 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 wb_mem_man:mem_man|out1_6 } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "9.135 ns" { rst G_271 wb_mem_man:mem_man|out1_6 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "9.135 ns" { rst rst~out0 G_271 wb_mem_man:mem_man|out1_6 } { 0.000ns 0.000ns 5.169ns 1.824ns } { 0.000ns 1.135ns 0.340ns 0.667ns } } } { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clk wb_mem_man:mem_man|out1_6 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 wb_mem_man:mem_man|out1_6 } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } } 0}{ "Info" "ITDB_FULL_TCO_RESULT" "clk out1\[7\] wb_mem_man:mem_man\|out1_7 6.094 ns register " "Info: tco from clock \"clk\" to destination pin \"out1\[7\]\" through register \"wb_mem_man:mem_man\|out1_7\" is 6.094 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.248 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.248 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 126 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 126; CLK Node = 'clk'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { clk } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2936 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.571 ns) + CELL(0.547 ns) 2.248 ns wb_mem_man:mem_man\|out1_7 2 REG LC_X11_Y11_N7 1 " "Info: 2: + IC(0.571 ns) + CELL(0.547 ns) = 2.248 ns; Loc. = LC_X11_Y11_N7; Fanout = 1; REG Node = 'wb_mem_man:mem_man\|out1_7'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.118 ns" { clk wb_mem_man:mem_man|out1_7 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 324 16 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 74.60 % " "Info: Total cell delay = 1.677 ns ( 74.60 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.571 ns 25.40 % " "Info: Total interconnect delay = 0.571 ns ( 25.40 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.248 ns" { clk wb_mem_man:mem_man|out1_7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.248 ns" { clk clk~out0 wb_mem_man:mem_man|out1_7 } { 0.000ns 0.000ns 0.571ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 324 16 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.673 ns + Longest register pin " "Info: + Longest register to pin delay is 3.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns wb_mem_man:mem_man\|out1_7 1 REG LC_X11_Y11_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y11_N7; Fanout = 1; REG Node = 'wb_mem_man:mem_man\|out1_7'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { wb_mem_man:mem_man|out1_7 } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 324 16 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.051 ns) + CELL(1.622 ns) 3.673 ns out1\[7\] 2 PIN PIN_78 0 " "Info: 2: + IC(2.051 ns) + CELL(1.622 ns) = 3.673 ns; Loc. = PIN_78; Fanout = 0; PIN Node = 'out1\[7\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "3.673 ns" { wb_mem_man:mem_man|out1_7 out1[7] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2942 52 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns 44.16 % " "Info: Total cell delay = 1.622 ns ( 44.16 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.051 ns 55.84 % " "Info: Total interconnect delay = 2.051 ns ( 55.84% )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "3.673 ns" { wb_mem_man:mem_man|out1_7 out1[7] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.673 ns" { wb_mem_man:mem_man|out1_7 out1[7] } { 0.000ns 2.051ns } { 0.000ns 1.622ns } } } } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.248 ns" { clk wb_mem_man:mem_man|out1_7 } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.248 ns" { clk clk~out0 wb_mem_man:mem_man|out1_7 } { 0.000ns 0.000ns 0.571ns } {0.000ns 1.130ns 0.547ns } } } { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "3.673 ns" { wb_mem_man:mem_man|out1_7 out1[7] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.673 ns" { wb_mem_man:mem_man|out1_7 out1[7] } { 0.000ns 2.051ns } { 0.000ns 1.622ns } } } } 0}{ "Info" "ITDB_TH_RESULT" "wb_mem_man:mem_man\|reg_in0\[3\] in0\[3\] clk -0.541 ns register " "Info: th for register \"wb_mem_man:mem_man\|reg_in0\[3\]\" (data pin = \"in0\[3\]\", clock pin = \"clk\") is -0.541 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.271 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 126 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 126; CLK Node = 'clk'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { clk } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2936 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns wb_mem_man:mem_man\|reg_in0\[3\] 2 REG LC_X16_Y13_N3 1 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X16_Y13_N3; Fanout = 1; REG Node = 'wb_mem_man:mem_man\|reg_in0\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.141 ns" { clk wb_mem_man:mem_man|reg_in0[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 498 20 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns 73.84 % " "Info: Total cell delay = 1.677 ns ( 73.84 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns 26.16 % " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clkwb_mem_man:mem_man|reg_in0[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 wb_mem_man:mem_man|reg_in0[3] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.012 ns + " "Info: + Micro hold delay of destination is 0.012 ns" { } { { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 498 20 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.824 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.824 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns in0\[3\] 1 PIN PIN_153 1 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_153; Fanout = 1; PIN Node = 'in0\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "" { in0[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 2939 18 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.605 ns) + CELL(0.089 ns) 2.824 ns wb_mem_man:mem_man\|reg_in0\[3\] 2 REG LC_X16_Y13_N3 1 " "Info: 2: + IC(1.605 ns) + CELL(0.089 ns) = 2.824 ns; Loc. = LC_X16_Y13_N3; Fanout = 1; REG Node = 'wb_mem_man:mem_man\|reg_in0\[3\]'" { } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "1.694 ns" { in0[3] wb_mem_man:mem_man|reg_in0[3] } "NODE_NAME" } "" } } { "../SYN/rev_1/ClaiRISC_core.vqm" "" { Text "D:/LWRISC/SYN/rev_1/ClaiRISC_core.vqm" 498 20 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.219 ns 43.17 % " "Info: Total cell delay = 1.219 ns ( 43.17 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.605 ns 56.83 % " "Info: Total interconnect delay = 1.605 ns ( 56.83 % )" { } { } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.824 ns" { in0[3] wb_mem_man:mem_man|reg_in0[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.824 ns" { in0[3] in0[3]~out0 wb_mem_man:mem_man|reg_in0[3] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 1.130ns 0.089ns } } } } 0} } { { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.271 ns" { clk wb_mem_man:mem_man|reg_in0[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.271 ns" { clk clk~out0 wb_mem_man:mem_man|reg_in0[3] } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } } } { "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" "" { Report "D:/LWRISC/QU2/db/ClaiRISC_core_cmp.qrpt" Compiler "ClaiRISC_core" "UNKNOWN" "V1" "D:/LWRISC/QU2/db/ClaiRISC.quartus_db" { Floorplan "D:/LWRISC/QU2/" "" "2.824 ns" { in0[3] wb_mem_man:mem_man|reg_in0[3] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.824 ns" { in0[3] in0[3]~out0 wb_mem_man:mem_man|reg_in0[3] } { 0.000ns 0.000ns 1.605ns } { 0.000ns 1.130ns 0.089ns } } } } 0}{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 10 16:27:23 2008 " "Info: Processing ended: Mon Mar 10 16:27:23 2008" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}